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Add writing to I2CR EEPROM using repeated addressing and performing
length separate write transactions of one byte each.
Relates-to: ELB-1402
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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Related-to: ELB-1299
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
(cherry picked from commit f53846c29f76ccee0141f6902703bb6855b14b6a)
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This adds basic support for the new Micrel KSZ9131 phy.
Related-to: ELB-1299
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
(cherry picked from commit cc96ed419f7585db15855dd53046562aadece3fb)
(cherry picked from commit 150e6b7f6c9c8342997245be50f3bc58df78aaf3)
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Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
(cherry picked from commit 28491c802d36accbb4d8562114ce8085ca53e1b0)
(cherry picked from commit 9ee5759d22acc3406bca3b76cb24ed558b64d0df)
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When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.
Fixes: ad8c43cbcafb ("net: dm: fec: Support the phy-supply
binding")
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
(cherry picked from commit 8f1a5ac797baac5b40f93eac80a7810f0a771ecf)
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Configure the phy regulator if defined by the "phy-supply" DT phandle.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
(cherry picked from commit ad8c43cbcafbbb21efc9e26bda7a6b1e37428adc)
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This adds the possibility to add a delay after a reset in DT.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
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The DT binding says:
- phy-reset-duration : Reset duration in milliseconds. Should present
only if property "phy-reset-gpios" is available. Missing the property
will have the duration be 1 millisecond. Numbers greater than 1000 are
invalid and 1 millisecond will be used instead.
However the current code:
- clamps values greater than 1000ms to 1000ms rather than 1.
- does not initialize the delay if the property does not exist
(else clause mismatch)
- returns an error if phy-reset-gpios is not defined
Fix all this and simplify by using dev_read_u32_default()
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
(cherry picked from commit 331fcabe4f9b4c7ec58d070da039f875673c9c9d)
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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The DT binding says that phy-reset-duration is in ms, but the driver
currently uses udelay().
Switch to mdelay() to fix this.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
(cherry picked from commit 9b8b91888493d25873b835d262b89f1c4efa0df7)
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Add the missing gpio phy reset binding to the gpio and
reset time configuration
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
(cherry picked from commit efd0b791069af93e9d439a70d1fe2ae8994dbbfa)
Conflicts:
drivers/net/fec_mxc.c
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Target mmc dev is not properly switched when the device enters
fastboot mode via uuu "-i" parameter, which causes "erase"
operation doesn't work.
Get and switch the target mmc dev every time before erase operations
happen.
Test: "fastboot erase boot_a" in uuu fastboot mode.
Change-Id: I4822d2b4ecfd2d874dfbe7474d6824b8fc3a7903
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Sync SCFW API to commit 6dcd0242ae
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
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To enable HS400 and UHS for imx8m platforms, update the driver data
to share with imx8x platforms and add relevant compatible string.
Signed-off-by: Ye Li <ye.li@nxp.com>
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In mmc initial state, the mmc framework sets clock to 0, so the fsl_esdhc
driver converts to use min clock 400Khz. But the priv->clock is logged
400Khz not 0, and cause following calls to set_ios to set clock again.
Each set to clock has 10ms delay for stable, then the problem accumulates
some unnecessary delay.
Signed-off-by: Ye Li <ye.li@nxp.com>
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PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
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ROM update emmc offset to 0.
previous B0 is 32K.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Set MCR0 RXCLKSRC to 1 to enable DQS loopback from pad to support
higher frequency.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The A/B slot selection is moved to spl, it may lead to hang
if no bootable slots found. The only way to recover the board
is re-flash images with uuu tool, which is quite inconvenient
for some customers who can't enter serial download mode.
This patch will set "spl recovery mode" which will give us a
chance to re-flash images with fastboot commands.
Test: Enter spl recovery mode and flash images when no bootable
slots found.
Change-Id: I31278f5212bde7609fe2f49e77b3849e92c0c516
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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when conduct fastboot lock/unlock operations, erase the userdata first
and then set lock/unlock status to improve security level.
Change-Id: I74c571c35b88afd6fdd4c287463f7209da8c15ff
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
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It can be dangerous to export some hwcrypto commands to Linux,
add commands to limit some commands within bootloader.
Test: hwcrypto commands can't be used after locking boot state.
Change-Id: Ib0a96a87f661778c133178840d8dccf49f151c22
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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In host end, need encrypt the attestation keys and certs
by manufacture protection public key though AES-128-ECB.
Then use below 4 set of commands to provision encrypted
RSA attestation and EC attestation:
* $fastboot stage atte_rsa_key.bin
* $fastboot oem set-rsa-atte-key-enc
* $fastboot stage atte_rsa_cert.bin
* $fastboot oem append-rsa-atte-cert-enc
* $fastboot stage atte_ec_key.bin
* $fastboot oem set-ec-atte-key-enc
* $fastboot stage atte_ec_cert.bin
* $fastboot oem append-ec-atte-cert-enc
Change-Id: I8a7c64004a17f7dde89f28c3123a2e2b1a6d3346
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
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Add new keymaster commands to get Manufacure Production key (mppubk).
Since the mppubk can only be generated in OEM CLOSED imx8q board, so
we can only this command when the board is HAB/AHAB closed.
Commands to extract the mppubk:
* $fastboot oem get-mppubk
* $fastboot get_staged mppubk.bin
Test: Generate and dump the mppubk.bin
Change-Id: Idc59e78ca6345497e744162664b8293f50d1eda4
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add configs to support evk_imx8mm 4GB DDR board. The 4GB DDR will
be split into two banks, one is 3GB (0x4000_0000~0xffff_0000) and
another is 1GB(0x1_0000_0000~0x1_4000_0000).
Test: build and boot with or without trusty.
Change-Id: I02f6465fc5709b15fd76820edb846452d011dd56
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Follow Bootloader requirement spec in
https://source.android.com/devices/bootloader/unlock-trusty.
Need to pass the flash lock status by androidboot.flash.locked.
This patch fixed the GTS failure
com.google.android.gts.persistentdata.PersistentDataHostTest#testTestGetFlashLockState.
Change-Id: I9a3508f7546b02c998e7668df2a33f864a58db75
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
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The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.
This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
(cherry picked from commit 8ff4130debcc09594b550209c44abf6c7e3ee595)
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new imx8mn chips have Cortex-M7 inside, not like any other existing
multi-core i.MX MPU, users may manually flash mcu firmware with
fastboot, partition name need to be specified at the same time, so the
mcu firmware partition name need to be changed. related enum and
variable names are also modified.
Change-Id: Ic7b0f3ff5faaeb92d79ad6f4d9d5546a83b95b5b
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
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We set SPL bss section on OCRAM. So move the g_jrdata to bss section
only on SPL. In normal u-boot, it is still in data section to avoid
overlay with relocation entries and DTB.
Signed-off-by: Ye Li <ye.li@nxp.com>
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This reverts commit b12e170792c918efc7c371f86989d34fc397fe06.
The original patch has issue due to the early malloc pool is not ready
at this phase. So malloc always return NULL.
Signed-off-by: Ye Li <ye.li@nxp.com>
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There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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The bootloader offset of SD and eMMC user area on imx8mn is 32KB.
When booting from eMMC boot0 or boot1 partition, no matter normal boot
or fastboot, the image offset is 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the IMX8MN to the EHCI-MX7 kconfig dependency.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the IMX8MN to the SEC MIPI DSI kconfig dependency, and
update display GPR registers for iMX8MN changes.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add is_imx8mn for runtime soc type checking, and update drivers to use it.
Signed-off-by: Ye Li <ye.li@nxp.com>
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On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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We have initialized pre_div, so no need to override it. And
it will break those have pre_div initialized as 2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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CONFIG_ANDROID_AB_SUPPORT
enlarge max bootargs number from 32 to 64 to align imx8 devices.
refine the usage of CONFIG_ANDROID_AB_SUPPORT and CONFIG_SYSTEM_RAMDISK_SUPPORT
Change-Id: I4cef6d87559e0881460c37bde202b35037e3110a
Signed-off-by: zhang sanshan <pete.zhang@nxp.com>
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The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM
devices.
Due to different cache management it's necessary to flush dcache
range for destination address so data can be available in memory.
Add necessary operations in blob_encap() and blob_decap() functions.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to
non-TrustZone") breaks HABv4 encrypted boot support in the
following i.MX devices:
- i.MX6UL
- i.MX7S
- i.MX7D
- i.MX7ULP
For preparing a HABv4 encrypted boot image it's necessary to
encapsulated the generated DEK in a blob. The blob generation
function takes into consideration the Job Ring TrustZone
ownership configuration (JROWN_NS) and can be only decapsulated
by the same configuration.
The ROM code expects DEK blobs encapsulated by the Secure World
environments which commonly have JROWN_NS = 0.
As U-Boot is running in Secure World we must have JROWN_NS=0
so the blobs generated by dek_blob tool can be decapsulated
by the ROM code.
As NXP BSP does not requires all job-rings assigned to
non-Secure world this commit can be safely reverted.
This reverts commit 22191ac353445ad8fafc5a78aefcd94e78963041.
Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
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After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.
During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true, make sure in the function
mmc_set_card_speed(), after switch to HS mode, first config the
clock rate, then read the EXT_CSD. Otherwise read EXT_CSD in HS mode
at wrong clock rate, e.g. 200MHz, may lead to uncertain result.
Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.
Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
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The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.
In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.
However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
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Fix coverity issue: CID 2970630: Resource leak (RESOURCE_LEAK)
leaked_storage: Variable cdns going out of scope leaks the storage
it points to.
Memory allocated by devm_kzalloc() won't be freed automatically in
u-boot, free the memory manually here.
Test: Coverity scan pass.
Change-Id: I3000a2385941cef3b8b7e01611cfdc999971a4ca
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Fix coverity issue:
CID 43787: Buffer not null terminated (BUFFER_SIZE_WARNING)
buffer_size_warning: Calling strncpy with a maximum size argument
of 32 bytes on destination array sdev.name of size 32 bytes might
leave the destination string unterminated.
Test: Coverity scan pass.
Change-Id: Ib10e631bab893cb9cd1484082229f806b02849ba
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Fix coverity issue: CID 1477258: Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value txbuf when calling __fswab32.
Test: Coverity scan pass.
Change-Id: If57f70c272ef49a6636a59ae3b5dcc5430fd1753
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Trusty is not supported for xen so we don't need to check
the keyslot package or rollback index in spl. Reassign the
dram address for spl and u-boot to avoid conflicts.
Support serial init functions to enable debug console
in spl when xen is running.
Test: Boot and A/B slot switch on imx8qm_mek.
Change-Id: If6829252f1ec2e32255f951715c8747181951fd0
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Currenlty U1 and U2 low power modes are allowed in device mode.
Allowing U1 and U2 low power modes during data transfers in
device mode is causing U1 exit failure on some USB3 host: which
will transite to SS.inactive instead of U0, then host will send
warm reset and ultimately result in reenumeration. This is observed
on UUU tool with some PC host. Hence disable U1 and U2 low power
modes for now.
USB3 spec 7.5.10.4.2 Exit from Recovery.Configuration
The port shall transition to eSS.Inactive when the following
conditions are met:
1. Either the Ux_EXIT_TIMER or the 6-ms timer
(tRecoveryConfigurationTimeout) times out.
2. For a downstream port, the transition to Recovery is not to
attempt a Hot Reset.
Signed-off-by: Li Jun <jun.li@nxp.com>
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The HDMI digital PLL, bus clock and core clock need to change to improve the
firmware loading time. The clock are now set to 800 MHz for DPLL, 200 MHz for
HDMI core, and 100 MHz for HDMI bus.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
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