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2018-01-21core: Make device_is_compatible live-tree compatibleMario Six
Judging from its name and parameters, device_is_compatible looks like it is compatible with a live device tree, but it actually isn't. Make it compatible with a live device tree. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21core: Add {ofnode, dev}_translate_address functionsMario Six
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21core: read: Fix style violationsMario Six
There are some whitespace-related style violations in read.c; fix those. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21core: ofnode: Fix style violationsMario Six
There are some style violations in ofnode.c; fix those. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: Makefile: Sort entries alphabeticallyMario Six
The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: Remove superfluous gd declarationsMario Six
The clk uclass was converted to support a live device tree recently, hence the global data pointer declarations are no longer needed. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: clk_fixed_rate: Fix style violationMario Six
Fix a mis-indented function call in clk_fixed_rate.c Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21clk: clk-uclass: Fix style violationsMario Six
checkpatch.pl complains that the clk_ops structures used in clk-uclass.c ought to be const, so we mark them as const. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21drivers: core: Add translation in live tree caseMario Six
The function dev_read_addr calls ofnode_get_addr_index in the live tree case, which does not apply bus translations to the address read from the device tree. This results in illegal addresses on boards that rely on bus translations being applied. Fix this situation by applying bus translations in the live tree case as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Tested-by: Stephen Warren <swarren@nvidia.com>
2018-01-20Merge git://git.denx.de/u-boot-marvellTom Rini
2018-01-19Merge git://git.denx.de/u-boot-arcTom Rini
2018-01-19serial: stm32: Rename serial_stm32x7.c to serial_stm32.cPatrice Chotard
Now this driver is used across stm32f4, stm32f7 and stm32h7 SoCs family, give it a generic name. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-01-19GPIO: tca642x: Rework to not include commands in SPLTom Rini
The command portion of the GPIO driver can only be used in full SPL so re-work to guard the command related portions and mark it as static. Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-19GPIO: pca953x: Rework to not include commands in SPLTom Rini
The command portion of the GPIO driver can only be used in full SPL so re-work to guard the command related portions and mark it as static. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19drivers: dma: ti-edma3: add support for memory fillTero Kristo
Add support for simple memory fill operation. With large data sizes it is much faster to use EDMA for memory fill rather than CPU. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-01-19mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bitKishon Vijay Abraham I
omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Enable Auto command (CMD12) enableKishon Vijay Abraham I
Instead of sending STOP TRANSMISSION command from MMC core, enable the auto command feature so that the Host Controller issues CMD12 automatically when last block transfer is completed. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19mmc: omap_hsmmc: Add support for DMA (ADMA2)Kishon Vijay Abraham I
The omap hsmmc host controller can have the ADMA2 feature. It brings better read and write throughput. On most SOC, the capability is read from the hl_hwinfo register. On OMAP3, DMA support is compiled out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19ddr: marvell: update ddr controller init and freqChris Packham
Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19ddr: marvell: update additional ODT settingChris Packham
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f instead of 0xf. Rather than checking the read sample delay for all DDR chip selects use the values for the chip selects that are actually configured. Finally continue searching for the max_phase value even if the current read_sample is the same as the max_read_sample. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19ddr: marvell: use correct TREFI valueChris Packham
The ternary operation had the HIGH/LOW values the wrong way round. Update it to use the correct value. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19ddr: marvell: only assert M_ODT[0] on write for a single CSChris Packham
When using only a single DDR chip select only assert M_ODT[0] on write. Do not assert it on read and do not assert M_ODT[1] at all. Also set tODT_OFF_WR to 0x9 which contradicts the recommendation from the functional spec but is what Marvell's binary training blob does and seems to give better results when ODT is active during writes. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19ARC: HSDK: CGU: Add 'Hz' when printing clock frequencyEugeniy Paltsev
Add 'Hz' when printing clock frequency in error messages. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19ARC: HSDK: CGU: Use plat data instead of priv dataEugeniy Paltsev
Correctly allocate hsdk_cgu_clk private data structure using priv_auto_alloc_size instead of platdata_auto_alloc_size. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19ARC: HSDK: CGU: Update AXI, TUN, ARC clock optionsEugeniy Paltsev
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-18Revert "omap_hsmmc: update struct hsmmc to accommodate omap3 from DT"Jean-Jacques Hiblot
This reverts commit 46831c1a4cda75d92f7ad18d4e2b1eb196c62b2f. This reserved area at the beginning of struct hsmm, will be used later to support ADMA Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-17Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-01-16i2c: mxc_i2c: Use or operationPeng Fan
The operation should be OR, not BIT OR. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-01-16i2c: lpi2c: do not add 4 for bus seqPeng Fan
The number 4 is dedicated on i.MX7ULP, but lpi2c will be reused on i.MX8, 4 is not valid. The seq number could be configured by alias node. The following patch will use i2c4 as the begin for i.MX7ULP. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-15Merge git://git.denx.de/u-boot-netTom Rini
2018-01-15Merge git://git.denx.de/u-boot-imxTom Rini
2018-01-15db410c: replace reset driver with psciJorge Ramirez-Ortiz
this should be the norm for armv8 platforms. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15db820c: enable pmic gpios for pm8994Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15serial: lpuart: Proper device identificationSriram Dash
Identify and distinguish between platform device type of MX7ULP and LS1021A. This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP support"). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15phy: atheros: set auto-negotiation for AR8021Zhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Add to Kconfig and convertNobuhiro Iwamatsu
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Fix misaligned cache operation warningNobuhiro Iwamatsu
When we using network on board using sh-eth, it prints a lot of "CACHE: Misaligned operation at range" messages. This commit fixes this problem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Change read/write() param to struct sh_eth_infoNobuhiro Iwamatsu
This changes Change structure used in sh_eth_read and sh_eth_write function from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert to Driver Model. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Remove bd_t from sh_eth_config()Nobuhiro Iwamatsu
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config() Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: Fix coding style checked by checkpatch.plNobuhiro Iwamatsu
This fixes the chord style checked by checkpatch.pl. Details of change details are as follows: - Fix typo Change from alligned to aligned. - Remove whitespace before ',' - Add spaces preferred around that '|' - Fix missing a blank line after declarations - Remove space after a cast declaration - Fix format of block comments - Add a blank line after function/struct/union/enum declarations Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: phy: b53: Add b53_reg read/write commandsFlorian Fainelli
Add a b53_reg read/write command which allows inspecting the switch registers. Because the Broadcom BCM53xx registers have different sizes, we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain expected results. Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: designware: Pad small packetsFlorian Fainelli
Make sure that we pad small packets to a minimum length of 60 bytes (without FCS). This is necessary to interface with Ethernet switches that will reject RUNT frames unless padded correctly. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: phy: Add Broadcom BCM53xx switch driverFlorian Fainelli
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar to the Marvell MV88E617x. This takes care of configuring the minimum amount out of the switch hardware such that each user visible port (configurable) and the CPU port can forward packets between each other while preserving isolation with other ports. This is useful for e.g: the Lamobo R1 board featuring a Broadcom BCM53125 switch. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15net: designware: add clock supportPatrice Chotard
This implementation manages several clocks, disable and free all of them in case of error during probe and in remove callback. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15dm: core: add missing dev_count_phandle_with_args()Patrice Chotard
Add missing dev_count_phandle_with_args() to avoid compilation issue. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: mvneta - Fixed recv() when multiple packets have arrived.Jason Brown
This patch fixes a problem in the mvneta driver where if more than one packet arrives between calls to mvneta_recv(), the additional descriptors will be marked as free even though only one descriptor has been read and processed from the receive queue. This causes the additional packet(s) to be delayed until the next packet arrives. >From this point on all packets will be delayed because the receive queue will contain unprocessed packets but the hardware shows no busy descriptors. Signed-off-by: Jason Brown <jason.brown@apcon.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: miiphybb: fix casting errorChris Brandt
Since the return value is a signed int, if the leading MSB of rdreg is a 1, it will get signed extended and will return a negative value which is an error even though we read the correct value. Fixes: dfcc496ed7e2 ("net: mii: Changes not made by spatch") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: remove sh_eth_offset_rz tableChris Brandt
First, this table could never be included in the build anyway because SH_ETH_TYPE_RZ is not defined until later in the file. Second, the register PIR was missing, so PHY MDIO never worked. Third, after adding the PIR register, the table is EXACTLY the same as sh_eth_offset_gigabit, so there is no value to it. Therefore, just delete it use the gigabit one. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: sh-eth: fix inl and outl definitionsChris Brandt
The macros inl and outl maybe already be defined from file arch/arm/include/asm/io.h so there may be no reason to define them. And if you do try defined them here, you get a redefined complier warning. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15net: phy: marvell: Add functions to read PHY's extended registersLukasz Majewski
This commit allows extended Marvell registers to be read with: foo > mdio rx FEC 3.10 Reading from bus FEC PHY at address 0: 3.16 - 0x1063 foo > mdio wx FEC 3.10 0x1011 The above code changes the way ETH connector LEDs blink. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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