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path: root/drivers/spi
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2015-10-27spi: ti_qspi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in ti_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: tegra: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in tegra*.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: sh_qspi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in sh_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: omap3_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in omap3_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: mpc8xxx_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in mpc8xxx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: ich: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in ich :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: fsl: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: designware_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in designware_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: cadence_qspi_apb: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: bfin_spi6xx: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in bfin_spi6xx :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: atmel_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in atmel_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: zynq_[q]spi: Use GENMASK macroJagan Teki
GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: zynq_[q]spi: Use BIT macroJagan Teki
Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_qspi: Minor cleanupsJagan Teki
- Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Remove unneeded headersJagan Teki
- Removed unneeded inclusion of header files - Add "Xilinx" on license text Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_qspi: Fix to configure CPOL, CPHA maskJagan Teki
priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Store cs value into private dataJagan Teki
Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Rename baudrate divisor mask nameJagan Teki
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Add config reg shift named macrosJagan Teki
Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: Kconfig: Add Zynq QSPI controller entryJagan Teki
Add Zynq QSPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-10-25spi: Add zynq qspi controller driverJagan Teki
Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-23spi : convert altera_spi to driver modelThomas Chou
Convert altera_spi to driver model Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-21x86: spi: Add support for Wildcat PointGeorge McCollister
Add the Wildcat Point ID so Broadwell U based boards can use SPI. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-11spi: tegra20: Add support for mode selectionMirza Krak
Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11spi: zynq_spi: Fix to configure CPOL, CPHA maskJagan Teki
priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11spi: xilinx_spi: Fix to configure CPOL, CPHA maskJagan Teki
priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-09-11bitops: introduce BIT() definitionHeiko Schocher
introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass
Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02rockchip: Add SPI driverSimon Glass
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-31dm: Use dev_get_addr() where possibleSimon Glass
This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-08-18Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2015-08-17spi: ti_qspi: Use DMA to read from qspi flashVignesh R
ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17ARM: exynos: move SoC sources to mach-exynosThomas Abraham
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-08-12spi: omap3_spi: add am43xx support to omap3_spiNikita Kiryanov
Add support for AM43XX to the omap3_spi driver. Cc: Jagan Teki <jteki@openedev.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-06lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t typeYork Sun
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated to %pa to match the type. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
2015-08-05exynos: spi: Convert the timeout to debug()Simon Glass
Since the timeout is reported through normal channels, and is sometimes expected (e.g. if the bus is being probed for a non-existent device), don't display the message in the driver. In general, drivers should not write to the console as this limits their usefulness in error conditions. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-28spi: zynq_spi: Simplify debug macroMichal Simek
Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28spi: Fix zynq SPI bindingMichal Simek
Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-21dm: spi: Make local functions staticSimon Glass
Several functions in this file should be marked as static. Update them. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-20fdt: armv8: Fix build warnings on armv8Haikun Wang
Fix below build warnings on armv8, drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’: drivers/spi/fsl_dspi.c:667:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘fdt_addr_t’ [-Wformat=] debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n", ^ lib/fdtdec.c: In function ‘fdtdec_get_addr_size’: lib/fdtdec.c:105:4: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=] debug("addr=%08lx, size=%08lx\n", ^ Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-15Merge git://git.denx.de/u-boot-x86Tom Rini
2015-07-14dm: spi: Correct BIOS protection logic for ICH9Simon Glass
The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
2015-07-14dm: spi: Correct status register access widthSimon Glass
The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14dm: spi: Correct minor nits in ICH driverSimon Glass
Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-03spi: cadence_qspi: support FIFO width other than 4 bytesVikas Manocha
This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03spi: cadence_qspi: get sram size from device treeVikas Manocha
sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03spi: cadence_qspi: move the sram partition in initVikas Manocha
There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-01spi: cf_qspi: fix clamp macro type check compilation warningsAngelo Dureghello
Fix compilation warnings for redefined 'clamp' macro and non-uniform clamp macro types. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-01spi: Kconfig: Add TEGRA20_SLINK entryJagan Teki
Added TEGRA20_SLINK entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
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