summaryrefslogtreecommitdiff
path: root/drivers/ram
AgeCommit message (Collapse)Author
2024-03-21ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_sizeSanthosh Kumar K
The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for AM64x, AM62x and AM62x SIP. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Acked-by: Bryan Brattlof <bb@ti.com>
2024-03-21ram: k3-ddrss: ram_ops should be a constantBryan Brattlof
I do not think the R5 SPL will initialize non static variables (I didn't find and evidence of it) so we want to ensure this is a constant. Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-21ram: k3-ddrss: limit only the am64x addressable rangeBryan Brattlof
The AM64x and some of the AM62xx family of devices use the same 16b controller though only the AM64x is limited to 2GB addressable. Annoyingly the address alias detection machinery defaults to the full 8GB for the AM64x. Reset this value to 2GB only if we're initializin DDR on an am64x device Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-21drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECCNeha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL only when the config has been enabled. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2024-03-21ram: k3-ddrss: Enable ECC interruptsSanthosh Kumar K
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts by setting the respective bits in the DDRSS_V2A_INT_SET_REG register. Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2024-03-21ram: k3-ddrss: Setup ECC region start and rangeSanthosh Kumar K
Setup the ECC region's start and range using the device private data, ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and range of ECC regions from 32 bits to 64 bits to accommodate for DDR greater than or equal to 4GB. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-03-21ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations ↵Santhosh Kumar K
restricted to 32 bits' issue As R5 is a 32 bit processor, the RAM banks' base and size calculation is restricted to 32 bits, which results in wrong values if bank's base is greater than 32 bits or bank's size is greater than or equal to 4GB. So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and size of RAM's banks from the device tree memory node, and store in a 64 bit device private data which can be used for ECC reserved memory calculation, Setting ECC range and Fixing up bank size in device tree when ECC is enabled. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-03-21ram: k3-ddrss: Use the DDR controller BIST engine for ECC primingGeorgi Vlaev
The 1-bit inline ECC support in TI's DDRSS bridge requires the configured memory regions to be preloaded with a pattern before use. This is done by the k3-ddrss driver from the R5 SPL in a 'for' loop. It takes around 10 seconds to fill 2GB of memory, for example. Memset can cut the time in half and using DMA currently yields a similar result. The BIST engine of DDR controller provides support for initializing any memory region with a pattern. This bypasses the DDRSS bridge, so the required inline ECC data is not computed and populated in the memory. For some values like zero, the computed ECC syndrome is also zero and we can use these values to preload the memory from the DDR controller, without the assistance of the bridge. The registers involved in the process are described in the 'DDR controller registers' topic in [1] AM62 and [2] J721E reference manuals. The patch replaces the 'for' loop memory fill function with the BIST memory initialization procedure. This cuts the time to preload the 2GB memory from 10 seconds down to 1 second. The bist preload function uses the lpddr4 APIs in the k3-ddrss, so this is compatible with devices with both 16-bit LPDDR4 and 32-bit LPDDR4 interfaces (e.g J721E). [1] AM62x: https://www.ti.com/lit/pdf/spruiv7 [2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1 Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-03-21ram: k3-ddrss: Enable the am62ax's DDR controller for J722SJayesh Choudhary
The J722S family of SoCs uses the same DDR controller as found on the AM62A family. Enable this option when building for the J722S family. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2023-11-28ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof
commit af7c33c103450e06aecf8adba8cbc8c522295be1 upstream. During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> [praneeth@ti.com: cherrypick from v2023.10] Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
2023-10-24ram: k3-ddrss: enable the am62ax's DDR controller for am62pxBryan Brattlof
The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-08-30ram: k3-ddrss: k3-ddrss: Fix updating ddr size with ecc offNitin Yadav
When DDR ECC is off (ecc_reserved_space = 0) k3_ddrss_ddr_fdt_fixup() doesn't update the DDR size in the memory node of DT. Fix this by dropping check for ecc_reserved_space to be non zero. This allows R5 SPL to fixup A53 SPL DT with right DDR size as discovered during DDR init or based on R5 SPL DT input. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nitin Yadav <n-yadav@ti.com>
2023-04-13ram: k3-ddrss: Add support for J784S4 SoCHari Nagalla
Add support for DDR subsystem in J784S4 SoC. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2023-04-02rockchip: Fix incorrect constant name in RAM init codeDavid Sebek
A condition in the rk3399 RAM initialization code used the old CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant. Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16ram: rockchip: Add rv1126 lpddr4 supportJagan Teki
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr driver supportJagan Teki
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr loader paramsJagan Teki
Add DDR loader parameters for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr3 supportJagan Teki
Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Update ddr pctl regs for px30Jagan Teki
Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Compute ddr capacity based on grf splitJagan Teki
DDR chip capacity is computed based on GRF split in some Rockchip SoC's like PX30 and RV1126. Add split argument in ddr print info so-that the respective ddr driver will pass the grf split. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add common ddr type configsJagan Teki
We have common ddr types in rockchip or in general. So use the common ddr type names instead of per Rockchip SoC to avoid confusion. The respective ddr type names will use on the associated ddr SoC driver as these drivers are built per SoC at a time. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: Mark ram-uclass depend on TPL_DM or SPL_DMJagan Teki
ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-22global: Remove unused CONFIG symbolsTom Rini
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-09ram: k3-ddrss: add am62a controller supportBryan Brattlof
TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-09ram: k3-ddrss: add auto-generated macros for am62a supportBryan Brattlof
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Fix incorrect statement of the register pollingDylan Hung
The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-10-19ram: rockchip: fix typo in KConfig option labelQuentin Schulz
RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo. Fixes: 2db36c64bd5a ("ram: rockchip: px30: add a config-based ddr selection") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-18RAM: Add changes for i.MXRT11xx seriesJesse Taube
The i.MXRT11 series has different offsets for IOCR_MUX, it also can address 64MiB of SDRAM so add a macro for that. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-04ram: rk3399: Conduct memory training at 400MHzLee Jones
Currently the default initialisation frequency is 50MHz. Although this does appear to be suitable for some LPDDR4 RAM chips, training at this low frequency has been seen to cause Column errors, leading to Capacity check errors on others. Here we force RAM initialisation to happen at 400MHz before ramping up to the final value running value of 800MHz after everything has been successfully configured. Link: https://lore.kernel.org/u-boot/Yo4v3jUeHXTovjOH@google.com/ Suggested-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Michal Suchánek <msuchanek@suse.de>
2022-09-04ram: rk3399: Fix faulty frequency change reportsLee Jones
Frequency changes to 400MHz are presently reported as: lpddr4_set_rate_0: change freq to 400000000 mhz 0, 1 This is obviously wrong by 6 orders of magnitude. Ensure frequency changes are reported accurately. Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04ram: rk3399: Fix .set_rate_index() error handlingLee Jones
Functions pointed to by this op pointer can return non-zero values indicating an error. Ensure any error value is propagated back up the call-chain. Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04drivers: ram: rockchip: Fix dram channels calculation for rk3399Han Pengfei
Only add the dram channel when we finally setup it successfully at the last step. Signed-off-by: Han Pengfei <pengphei@foxmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-07-25arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654Andrew Davis
The first AM6x device was the AM654x, but being the first we named it just AM6, since more devices have come out with this same prefix we should switch it to the normal convention of using the full name of the first compatibility device the series. This makes what device we are talking about more clear and matches all the K3 devices added since. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-28tpl: Ensure all TPL symbols in Kconfig have some TPL dependencyTom Rini
Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-17ram: stm32mp1: add support of STM32MP13xPatrick Delaunay
Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-10arm: mach-k3: Introduce the basic files to support AM62Suman Anna
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-10ram: stm32mp1: Conditionally enable ASRMarek Vasut
Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-04-20ram: k3-ddrss: Allow use of dt provided initial frequencyDave Gerlach
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-20ram: k3-ddrss: Fix register name and explain its usageDominic Rath
The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
2022-04-18rockchip: rk3066: add sdram driverPaweł Jarosz
Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-04ram: k3-am654: Make VTT regulator optionalChristian Gmeiner
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04ram: k3-am654: Write all configuration valuesDominic Rath
Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-29 06:54:26 +0000