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path: root/drivers/pinctrl
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2019-06-29pinctrl: uniphier: Add SPI pin-mux settingsKunihiko Hayashi
Add pin-mux settings for SPI controller. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-12Merge tag 'u-boot-amlogic-20190612' of git://git.denx.de/u-boot-amlogicTom Rini
- pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups - pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB - pinctrl: meson: add support for getting pinmux status - pinctrl: meson-g12a: add support for drive-strength-microamp property
2019-06-12pinctrl: meson-gxbb: add hdmi related pinsMaxime Jourdan
The GXBB pinctrl is missing pins related to HDMI, namely hot plug detection (hpd) and I2C (sda + scl). This fixes HDMI support for GXBB in u-boot. Reported-by: Mohammad Rasim <mohammad.rasim96@gmail.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Mohammad Rasim <mohammad.rasim96@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson: g12a: add DS bank valueGuillaume La Roque
add drive-strength bank regiter and bit value for G12A SoC Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson: add support of drive-strength-microampGuillaume La Roque
drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-axg: add support for getting pinmux statusNeil Armstrong
In order to support the "pinmux status" command, use the common functions to get the pins count and names, and add the AXG specific function to get the current function from registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-gx: add support for getting pinmux statusNeil Armstrong
In order to support the "pinmux status" command, use the common functions to get the pins count and names, and add the GX specific function to get the current function from registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
2019-06-12pinctrl: meson: add common function to get pins nameNeil Armstrong
In order to support the "pinmux status" command, add common function to get pins count and pin name. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groupsNeil Armstrong
The GPIO_TEST_N was in the wrong pmx group table, move it back with the AO groups, GPIODV_18 was missing, add it back, and finally the GPIOCLK_* group names were missing. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-11pinctrl: imx: Define imx6_pinctrl_soc_info in .data sectionLukasz Majewski
This commit is necessary to be able to re-use the pinctrl code in early SPL to properly configure pins. The problem is that those "static" structures (without explicit initialization) are placed in the SDRAM area, which corresponds to u-boot proper (not even SPL). Hence, when one wants to configure pins before relocation via DTS/DM, the board hangs (imx6q SoC powered one) as only OCRAM area is available (0x009xxxxx). This commit prevents from this issue by moving the imx6_pinctrl_soc_info structure to data section (from BSS). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-05-08pinctrl: rockchip: Also move common set_schmitter func into per Soc fileDavid Wu
Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Clean the unused type and labelDavid Wu
As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pullDavid Wu
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_pull() func into per SocDavid Wu
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strengthDavid Wu
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_drive() func into per SocDavid Wu
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomuxDavid Wu
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_mux() into per SocDavid Wu
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Remove redundant spacesDavid Wu
Some files have the redundant spaces, remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Add pull-pin-default param and remove unused paramDavid Wu
Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"Kever Yang
This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-07pinctrl: renesas: Add RZ/A1 R7S72100 pin control driverMarek Vasut
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()Marek Vasut
This function is now replaced by common pin controller GPIO configuration functionality, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Implement gpio_request_enable/gpio_disable_freeMarek Vasut
Implement the gpio_request_enable/gpio_disable_free callbacks to let the GPIO driver call the pin control framework and let it reconfigure pins as GPIOs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpioMarek Vasut
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin as a GPIO to retain the pin configuration information. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: gpio: Add callback for configuring pin as GPIOMarek Vasut
Add callback to configure, and de-configure, pin as a GPIO on the pin controller side. This matches similar functionality in Linux and aims to replace the ad-hoc implementations present in U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-01Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - improved SPI driver for better read throughput - refactors initialisation of debug UART init - restructures header file paths - adds pinctrl improvements Adds Kever as a co-custodian.
2019-05-01Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imxTom Rini
Porting to DM and i.MX8 ------------------------ - warp7 to DM - kp_imx53 to DM - Warnings in DT - MX8QM support - colibri-imx6ull to DM - imx7d-pico to DM - ocotp for MX8
2019-05-01pinctrl: exit pinconfig_post_bind if there are no subnodesUrja Rannikko
This fixes RK3288 SPL hanging or hitting this assert: drivers/core/ofnode.c:183: ofnode_first_subnode: Assertion `ofnode_valid(node)' failed. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-04-25pinctrl: imx8: add i.MX8QM compatiblePeng Fan
Add i.MX8QM compatible Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-24Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-bootTom Rini
STM32 MCUs update: - DT rework and alignment with DT kernel v4.20 - mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20 - mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20 - configs: update for F746/769 boards
2019-04-24Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogicTom Rini
- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
2019-04-23pinctrl: add driver for MT8516Fabien Parent
Add Pinctrl driver for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23pinctrl: stm32: Add st,stm32f769-pinctrl compatible stringPatrice Chotard
Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23pinctrl: meson: add g12a supportJerome Brunet
Add pinctrl support for the Amlogic G12A SoC, which is very similar to the Amlogic AXG support but with an additionnal drive-strength register bank. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-13Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dmTom Rini
fdtdec tests and improvements for carve-outs pinctrl race-condition fix various other fixes in sandbox, sound, mkimage, etc.
2019-04-13Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mipsTom Rini
- mt76xx: add USB support, small fixes - ath79: small fixes, add support for QCA9563 SoC and AP152 reference board - mscc: small fixes, add network support for JR2 and ServalT SoCs - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs - MIPS: fix redundant relocation of initrd images
2019-04-12Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-bootTom Rini
stm32 patches for v2019.07-rc1 - Add trusted boot with TF-A for stm32mp1 - stm32mp1 dts files sync'ed with Linux version - add STM32MP1 Discovery boards (DK1 and DK2) - add STMFX gpio expander driver - misc improvement for stm3mp1 supports - rename stpmu1 to stpmic1 (official name) - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu) - add STM32 FMC2 NAND flash controller driver
2019-04-12drivers: fix typo for pinctrl qca953xRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverPatrick Delaunay
This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on UCLASS_PINCTRL and UCLASS_GPIO. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-11dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind()Patrick Delaunay
Some binding define child node gpio-controller without compatible property. This patch avoid to bind the pinconfig uclass to these node. For example, the binding for st,stm32-pinctrl (./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl) but without compatible (as it is not mandatory). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11dm: pinctrl: Avoid race condition on probe for UCLASS_PINCTRLPatrice Chotard
In case of system with several pin-controller device, probe the first UCLASS_PINCTRL by seq number (defined by alias) to avoid race condition with I2C PINCONTROL driver for GPIO expander (GPIO expander need I2C bus, I2C driver need PINCONFIG). Signed-off-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().Christoph Muellner
This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. As noted in the comment, the function pinctrl_decode_pin_config_dm() only served as a temporary solution. Since the function has no users anymore, we can remove it again. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various rmobile fixes
2019-04-10pinctrl: meson: axg: Fix PIN and BANK offsetsGuillaume La Roque
Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-09pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen3 pin control tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen2 pin control tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add TDSEL fixup for H2/E2 ES1.0 SoCsMarek Vasut
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783, has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement similar fix for U-Boot. The difference here is that the SoC ES matching has to be implemented manually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add R8A77965 pin control tablesMarek Vasut
Add pin control tables for R8A77965 from Linux 5.0 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: at91: add slewrate support for SAM9X60Claudiu Beznea
Add slew rate support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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