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path: root/drivers/mtd/nand/atmel_nand.c
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2016-06-20Merge git://git.denx.de/u-boot-nand-flashTom Rini
2016-06-19mtd: nand: Patch remaining places where nand_to_mtd() should be usedBoris Brezillon
Some drivers are still directly accessing the chip->mtd field. Patch them to use nand_to_mtd() instead. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-12at91: nand: Set up the ECC strength correctlyAndre Renaud
This needs to be set to avoid a fatal error when ECC is used. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12at91: Correct NAND ECC register accessAndre Renaud
This uses the wrote base register value. Fix it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-03mtd: nand: Sync with Linux v4.6Scott Wood
Updates the NAND code to match Linux v4.6. The previous sync was from Linux v4.1 in commit d3963721d93fafa. Note that none of the individual NAND drivers tracked Linux closely enough to be synced themselves, other than manually applying a few cross-tree changes. Signed-off-by: Scott Wood <oss@buserror.net> Tested-by: Heiko Schocher <hs@denx.de>
2016-06-03mtd: nand: Add page argument to write_page() etc.Scott Wood
This change is part of the Linux 4.6 sync. It is being done before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03nand: Embed mtd_info in struct nand_chipScott Wood
nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03mtd: nand: Remove nand_info_t typedefScott Wood
This typedef serves no purpose other than causing confusion with struct nand_chip. Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-02atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu
Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-01-27atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic numberJosh Wu
As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the PMECC_OOB_RESERVED_BYTES. So use it in the driver. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2016-01-27atmel_nand: add '\n' in the end of error message for better displayJosh Wu
Also align the open parenthesis. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-01-27atmel_nand: use nand ecc_{strength, step}_ds instead of our own functionJosh Wu
Since ecc_{strength,step}_ds is introduced in nand_chip structure for minimum ecc requirements. So we can use them directly and remove our own get_onfi_ecc_param function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-08-12nand, atmel: remove udelay in spl_nand_erase_one()Heiko Schocher
remove unneeded udelay() in this function, as we use the dev_ready pin. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
2015-04-01ARM: at91: atmel_nand: Support flash based BBTDavid Dueck
Add support for on-flash bad block table. This makes U-Boot handle an existing BBT correctly. Signed-off-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Andreas Bießmann <andreas.devel@googlemail.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: Josh Wu <josh.wu@atmel.com>
2015-02-07mtd: atmel_nand: according to pmecc version to perform 0xff page correctionWu, Josh
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17mtd: atmel_nand: runtime to build gf table for pmeccJosh Wu
As in SAMA5D4 SoC, the gf table in ROM code can not be seen. So, when we try to use PMECC, we need to build it when do initialization. Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it is defined we will build gf table runtime. The PMECC use the BCH algorithm, so based on the build_gf_tables() function in lib/bch.c, we can build the Galois Field lookup table. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17spl, mtd, nand, atmel_nand: invert device ready pin logicHeiko Schocher
device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17spl, nand, atmel_nand: add erase one block functionHeiko Schocher
erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17mtd: atmel_nand: add missing includeHeiko Schocher
using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCBoris BREZILLON
Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-06-06mtd: nand: force NAND_CMD_READID onto 8-bit busBrian Norris
As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-03-09mtd: nand: atmel: prepare for nand spl boot supportBo Shen
Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-10Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
2013-12-09at91: nand: switch atmel_nand to generic GPIO APIAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Acked-by: Scott Wood <scottwood@freescale.com>
2013-11-21mtd: atmel_nand: use dev_xxx instead of printkWu, Josh
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21mtd: atmel_nand: don't print bit correction message in driverWu, Josh
Since for some MLC nand, bit errors happened too often. Just disable it to avoid noise Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-21mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flashWu, Josh
increase the delay to 75us to support the 8k bytes page nand flash Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-11-13MTD: atmel_nand: support for software BCH ECCBo Shen
Add possible to use software BCH ECC for atmel nand driver Signed-off-by: Bo Shen <voice.shen@gmail.com>
2013-09-04mtd: atmel_nand: pmecc: fix bug fail to correct bit error in 1024-bytes sectorWu, Josh
The PMECC use BCH algorithm to correct error. In BCH algorithm, the primitive polynomial value is GF(2^13) for 512-bytes sector size. And it is GF(2^14) for 1024-bytes sector size. This patch will choose correct degree of the remainders (13 or 14) for different sector size. Tested in AT91SAM9X5-EK with MLC nand flash. More detail can be refered to section 5.4.1 of: AT91SAM ARM-based Embedded MPU Application Note <http://www.atmel.com/Images/doc11127.pdf> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirementWu, Josh
1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's ecc minimum requirement in ONFI parameter. a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it. Driver will display a WARNING if the values are different from ONFI parameters. b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use the value from ONFI parameters. * If ONFI ECC parameters are in ONFI extended parameter page, since we are not support it, so assume the minimum ecc requirement is 2 bits in 512 bytes. * For non-ONFI support nand flash, also assume the minimum ecc requirement is 2 bits in 512 bytes. 2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP and CONFIG_PMECC_SECTOR_SIZE. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22mtd: atmel_nand: alloc memory instead of use static array for pmecc dataWu, Josh
In this way, the pmecc corraction capbility can change in run time. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-08-22ARM: at91: atmel_nand: pmecc driver will select the galois table by sector sizeWu, Josh
Define the galois index table offset in chip head file. So user do not need to set by himself. Driver will set it correctly according to sector_size. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> [rebased on master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-31mtd: resync with Linux-3.7.1Sergey Lapin
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-09-13atmel_nand: fix the U-Boot output information about nand flash with PMECC ↵Wu, Josh
enable. Before the patch, it looks like: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: Initialize PMECC params, cap: 2, sector: 512 > |256 MiB |MMC: mci: 0 |In: serial |Out: serial |Err: serial |Net: macb0 |Hit any key to stop autoboot: 0 After the patch: |U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11) | |CPU: AT91SAM9G35 |Crystal frequency: 12 MHz |CPU clock : 400 MHz |Master clock : 133.333 MHz |DRAM: 128 MiB |WARNING: Caches not enabled > |NAND: 256 MiB | ... ... |Hit any key to stop autoboot: 0 Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01at91: atmel_nand: Update driver to support Programmable Multibit ECC controllerWu, Josh
The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the PMECC correction capability, the sector size and ROM lookup table offsets in board config file. This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference is in this version it uses registers structure access hardware instead of using macros. It is tested in 9x5 serial boards. Signed-off-by: Josh Wu <josh.wu@atmel.com> [rebase] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01at91: atmel_nand: remove unused variables.Wu, Josh
Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01at91: atmel_nand: extract HWECC initialization code into one function: ↵Wu, Josh
atmel_hw_nand_init_param(). This patch 1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support. 2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix empty newline at EOF error and move return value check into ifdef] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-11-29Fix Stelian's email addressStelian Pop
Change my old email address which is no longer valid. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-04-01atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PINmichael
If NCE is hooked up to NCS3, we don't need to (and can't) explicitly set the state of the NCE pin. Instead, the controller asserts it automatically as part of a command/data access. Only "CE don't care"-type NAND chips can be used in this manner. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-01-12mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()Lei Wen
This patch sync with David's patch on Linux for handling nand_scan_ident. commit 5e81e88a4c140586d9212999cea683bcd66a15c6 Author: David Woodhouse <David.Woodhouse@intel.com> Date: Fri Feb 26 18:32:56 2010 +0000 mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident() Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
2010-03-23at91: add hwecc method for nandNikolay Petukhov
This is a patch to use the hardware ECC controller of the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
2009-03-22at91sam9/at91cap: move nand drivers to drivers/mtd/nandJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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