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path: root/drivers/gpio
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2022-05-23gpio: rgpio2p: Enhance reading of GPIO pin valueChristoph Fritz
Add support for reading GPIO pin value when function is output. With this patch applied, gpio toggle command is working. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-10gpio: stm32_gpio: Rework GPIO hole managementPatrice Chotard
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-05gpio: npcm: Add support for Nuvoton NPCM SoCsStanley Chu
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-05-03pci: Add mask parameter to dm_pci_map_bar()Andrew Scull
Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-03pci: Map bars with offset and lengthAndrew Scull
Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-02vpl: Add Kconfig options for VPLSimon Glass
Add VPL versions of commonly used Kconfig options. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-19gpio: aspeed: Fix incorrect offset of read back register.Billy Tsai
The offset of the current read back register is the value of the gpio pin, not the value written for the gpio output. This patch fix it to avoid the other gpio output value controlled by the same register being set incorrectly. Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver") Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
2022-04-08gpio: pca953x_gpio: add PCA957X supportLuca Ellero
Take as reference Linux kernel code: drivers/gpio/gpio-pca953x.c Signed-off-by: Luca Ellero <l.ellero@asem.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-08gpio: Enable hogging support in SPLEddie James
Use the CONFIG macros to conditionally build the GPIO hogging support in either the SPL or U-Boot, or both, depending on the configuration. Also call the GPIO hog probe function in the common SPL board initialization as an equivalent to adding it to the U-Boot init sequence functions. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-08gpio: Add gpio_request_by_line_name()Andrew Jeffery
Add support for the upstream gpio-line-names property already described in the common GPIO binding document[1]. The ability to search for a line name allows boards to lift the implementation of common GPIO behaviours away from specific line indexes on a GPIO controller. [1] https://github.com/devicetree-org/dt-schema/blob/3c35bfee83c2e38e2ae7af5f83eb89ca94a521e8/dtschema/schemas/gpio/gpio.yaml#L17 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05gpio: slg7xl45106: Update gpio desc flags from DTT Karthik Reddy
In current slg7xl45106 gpio driver xlate() function we are not updating gpio flags from DT. Read the given flag from DT and update the gpio desc flags variable with required gpio direction state. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8d7b4799337bd99f61ace509889f02b192a9414.1648631275.git.michal.simek@xilinx.com
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-04sunxi: pinctrl: Create the driver skeletonSamuel Holland
Create a do-nothing driver for each sunxi pin controller variant. Since only one driver can automatically bind to a DT node, since the GPIO driver already requires a manual binding process, and since the pinctrl driver needs access to some of the same information, refactor the GPIO driver to be bound by the pinctrl driver. This commit should cause no functional change. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01Convert CONFIG_BCM2835_GPIO to KconfigTom Rini
This converts the following to Kconfig: CONFIG_BCM2835_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-16Merge tag 'xilinx-for-v2022.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.07-rc1 microblaze: - Add support for reserved memory xilinx: - Update FRU code with MAC reading zynqmp: - Remove double AMS setting - DT updates (mostly for SOMs) - Add support for zcu106 rev 1.0 zynq: - Update nand binding nand: - Aligned zynq_nand to upstream DT binding net: - Add support for ethernet-phy-id mmc: - Workaround CD in zynq_sdhci driver also for ZynqMP - Add support for dynamic/run-time SD config for SOMs gpio: - Add driver for slg7xl45106 firmware: - Add support for dynamic SD config power-domain: - Update zynqmp driver with the latest firmware video: - Add skeleton driver for DP and DPDMA i2c: - Fix i2c to work with QEMU pinctrl: - Add driver for zynqmp pinctrl driver
2022-03-14Merge tag 'v2022.04-rc4' into nextTom Rini
Prepare v2022.04-rc4
2022-03-07gpio: Add Aspeed GPIO driverAndrew Jeffery
The Aspeed GPIO driver supports the GPIO controllers found in the AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down copy of the upstream Linux kernel driver, adapted for u-boot. Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2022-03-07gpio: bcm6345: allow to use this driver on arm bcm6753Philippe Reynes
This IP is also used on some arm SoC, so we allow to use it on arm bcm6753 too. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-07gpio: slg7xl45106: Add support for slg7xl45106 i2c gpo expanderT Karthik Reddy
slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by writing and reading corresponding gpo bit value into its data register. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com
2022-02-28gpio: add sl28cpld driverMichael Walle
The gpio block is part of the sl28cpld sl28cpld management controller. There are three different flavors: the usual input and output where the direction is configurable, but also input only and output only variants. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-05GPIO: fxl6408: Add support for FXL6408 GPIO expanderOleksandr Suvorov
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-01-30gpio: sunxi: Implement .set_flagsSamuel Holland
This, along with gpio_flags_xlate(), allows the GPIO driver to handle pull-up/down flags provided by consumer drivers or in the device tree. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-20Merge tag 'doc-2022-04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request doc-2022-04-rc1 Replace @return by Return: in code comments.
2022-01-19doc: replace @return by Return:Heinrich Schuchardt
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19Merge tag 'xilinx-for-v2022.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc1 gpio: - Add modepin driver net: - Save random mac addresses to eth variable zynqmp gem: - Add support for mdio bus DT description - Add support for reset and SGMII phy configuration - Reduce timeout for MDIO accesses zynqmp clk: - Fix clock handling for gem and usb phy: - Add zynqmp phy/serdes driver serial: - Add one missing compatible string microblaze: - Symbol alignement - SPL fixups - Code cleanups zynqmp: - Various dt changes, DP pre-reloc, gem resets, gem clocks - Switch SOM to shared psu configuration - Move dcache handling to firmware driver - Workaround gmii2rgmii DT description issue - Enable broadcasts again - Change firmware enablement logic - Small adjustement in firmware driver versal: - Support new mmc@ DT nodes - Fix run time variable handling - Add missing I2C_PMC ID for power domain
2022-01-16gpio: da8xx_gpio: Fix gpio name with addresschao zeng
The GPIO bank numbers do not appear in the device tree, so make the gpio name based on the address (ie gpio@42110000_25 vs 25) Signed-off-by: chao zeng <chao.zeng@siemens.com>
2022-01-05zynqmp: gpio: Add support for zynqmp gpio modepin driverT Karthik Reddy
ZynqMP modepin driver has capability to get/set/check status of modepin gpios. These modepins are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2021-12-27Convert CONFIG_KIRKWOOD_GPIO to KconfigTom Rini
This converts the following to Kconfig: CONFIG_KIRKWOOD_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-31SoC: exynos: add support for exynos 78x0Dzmitry Sankouski
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoCDzmitry Sankouski
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephan Gerhold <stephan@gerhold.net> [trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-20gpio: sifive: Fix -Wint-to-pointer-cast warningBin Meng
dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and plat->base is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-gpio.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-19drivers/gpio: add support for MAX7320 i2c i/o expanderHannes Schmelzer
This commit adds support for the MAX7320 (and clones) gpio expander. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2021-10-11sunxi: gpio: Remove bank-specific size macrosSamuel Holland
Since the beginning, all banks have had space for 32 pins, even when not all pins were implemented. Let's use a single constant for the GPIO bank size here, like the GPIO driver is already doing. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Clean up inclusions of asm/arch/gpio.hSamuel Holland
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11gpio: sunxi: Remove the sunxi_name_to_gpio_bank functionSamuel Holland
The only caller of this function was the MMC pinmux code, which used it to parse a string given from a Kconfig symbol. As the Kconfig symbol has been converted to a Boolean, this function is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-05gpio: Factor out DT flag translationSamuel Holland
The generic GPIO flags binding is shared across many drivers, some of which need their own xlate function. Factor out the flag translation code from gpio_xlate_offs_flags so it does not need to be duplicated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets from device treesSamuel Holland
Translation of an OF GPIO specifier should fail if the pin offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets when looking up namesSamuel Holland
Translation of a pin name to a device+offset should fail if the offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-01arm: Remove zmx25 board and ARCH_MX25Tom Rini
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well. Cc: Matthias Weisser <weisserm@arcor.de> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01arm: Remove aspenite boardTom Rini
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last armada100 platform, remove that support as well. Cc: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-30WS cleanup: remove excessive empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-25dm: gpio: Add of-platdata supportSimon Glass
Add support for accessing GPIOs using of-plata. This uses the same mechanism as for clocks, but allows use of the xlate() method so that the driver can interpret the parameters. Update the condition for GPIO_HOG so that it is not built into SPL, since it needs SPL_OF_REAL which is not enabled in sandbox_spl. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-13pci: Drop DM_PCISimon Glass
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04gpio: Add a GPIO configSimon Glass
At present we have SPL_GPIO and TPL_GPIO but not piain GPIO. This works because there is a special build rule in Makefile that always includes the drivers/gpio directory. It is better to have all driver directories included by drivers/Makefile and there is already a rule in there for this purpose. It just needs a Kconfig for U-Boot proper, so add one. Enable the option always for now, since this mimics current behaviour. This can be updated once DM_GPIO is used everywhere. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-20 06:29:43 +0000