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In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs,
the small value is the only value with the correct size. If it supports more,
if the number of sectors is small enough to fit into 28 bits, both fields
reflect the correct value. If it's too large, the smaller field has 28 bits of
1s, 0xfffffff, and the other field has the correct value.
The AHCI driver is implemented by attaching to the generic SCSI code and
translating on the fly between SCSI binary data structures and AHCI data
structures. It responds to requests to execute specific SCSI commands by
executing the equivalent AHCI commands and then crafting a response which
matches what a SCSI disk would send.
The AHCI driver now considers both fields and chooses the correct one when
implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands.
BUG=chrome-os-partner:8180
TEST=Built and booted to ChromeOS with this code on a CRB with a 250 GB drive
and a Stumpy with a 16 GB drive. Checked the serial output to make sure U-Boot
reported the correct size. Forced the READ CAPACITY (10) command to saturate
so that the READ CAPACITY (16) command would be used and verified that that
also booted correctly on a CRB.
Change-Id: I31b662498f4c9657d70bb90400032c83e9d9c8da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18061
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This command doesn't really do anything when talking to a SATA device, and
sending it confuses some of them. This change makes sending the command
optional, and defaults to not. The situations where it should be sent are not
the common case.
With the standard SSD in the machine, here are some times with the option
turned off:
1. 8277
2. 8273
3. 8050
And turned on:
1. 8303
2. 8155
3. 8276
Sending that command seems to have no meaningful effect on performance.
BUG=chrome-os-partner:7714
TEST=Booted off an SSD that hadn't worked with U-Boot previously. This SSD
was lent to us by Grant, and has chips labelled as Toshiba NV6424,
Taiwan 11159AE P, and TC58NVG5D2FTA10.
Change-Id: I750a6c7931a95a1529e0b99ee98528a549824ee4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14916
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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- remove unused ssleep macro
- add some useful debugging information
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=none
TEST=boot latest firmware on stumpy, no functional change.
Change-Id: Ieef3c199225b8c1aa979dfebf8a6f2178d5aa316
Reviewed-on: https://gerrit.chromium.org/gerrit/14836
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
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- print the correct speed
- print all the AHCI capability flags
(information taken from Linux kernel driver)
- clean up some comments
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=chrome-os-partner:7714
TEST=See the following string in bios_log:
AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
Change-Id: Ib32dbeddd0714359948e2bec033b2ec7aabbdb10
Reviewed-on: https://gerrit.chromium.org/gerrit/14754
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The "scsi write" command requires support from underlying driver.
This CL enables SCSI_WRITE10 in AHCI driver.
BUG=chrome-os-partner:6258
TEST=(enter U-BOOT console, try to i/o with sector #64)
scsi read 1000 40 1
md.b 1000 200 # check if things are not 0xcc
mw.b 1000 cc 200 # try to fill with 0xcc
scsi write 1000 40 1
mw.b 1000 0 200 # fill with zero
md.b 1000 200 # should be all 0
scsi read 1000 40 1
md.b 1000 200 # should be all 0xcc
Change-Id: Ib8d980c88c0d26894434ab62173877b8839d2891
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/9712
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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The existing code waits a whole second for the AHCI controller to reset.
Instead, let's poll the status register to see if the reset has
succeeded and return earlier if possible. This brings down the time for
AHCI probing from 1s to 20ms.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=none
TEST=boot coreboot/u-boot on lumpy and notice a boot time of 1.7s
Change-Id: I235ce027ed7a3ba999423700aec44fbbf94e8b68
Reviewed-on: http://gerrit.chromium.org/gerrit/8091
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
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First - make sure the ahci driver compiles and links properly when
building for x86 platforms.
Then it turned out that when trying to use AHCI driver on an x86
platform with an Intel AHCI controller, the driver does not operate
properly if the requested amount of blocks to read was exceeding 255.
It is probably possible to specify 0 as the block count and the driver
will read 256 blocks, but it was decided to limit the number of blocks
read at once to 128 (it should be a power of 2 for the optimal
performance of solid state drives).
BUG=chromium-os:19837
TEST=manual
. program updated image (including vbexport SATA support extension)
on an Alex.
. restart the machine and enter `vboot_twostop' at u-boot prompt.
Observe ChromeOS booting all the way to login screen.
Change-Id: I7224ca14ae60f414db6dbe9e2f0a649312a9459c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/7232
Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Before the actual initialization do a hard reset of the SATA port and the
connected device.
changes v1->v2:
- add comment for udelay
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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Faraday's ftide020_s is an IDE-AHB controller for SoC design.
This patch add the u-boot driver (PIO) of ftide020 ATA (IDE) driver.
IDE commands include read, info, and other functions has been implemented.
Because this IDE controller support AHB interface only which is differ
from other most IDE controller supports PCI interface. Some registers
access is required during CMD/DATA I/O. Hence a configuration
"CONFIG_IDE_AHB" is required to be defined according to the feature in
cmd_ide.c.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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Drop warnings due to unused variables.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
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Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
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mvsata_ide_initialize_port(): adjust init sequence (SStatus
should be checked only after all writes to SControl) and
return success/failure to ide_preinit().
Also, as some tests showed init durations in the hundreds
of us, raise the time-out to 01 ms to be on the safe side.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
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This driver only provides initialization code; actual driving
is done by cmd_ide.c using the ATA compatibility mode of the
Marvell SATAHC controller.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
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Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
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Rather than bang MMRs directly, use the new portmux framework to handle
the details.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Cast first parameter to sata_cpy()
In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(),
ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in
include/libata.h which is included in ata.h which is included by all files
which include ata_piix.h (only ata_piix.c) so these definitions are
supurflous to (and conlict with) this in libata.h. Interestingly, my
compiler complains about ata_id_u64 already being defined, but not
ata_id_u32
ata_dump_id() is defined in include/libata.h and should not be static
(maybe should even use ata_dump_id() in libata.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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"All Rights Reserved" conflicts with the GPL.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
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ahci.c: In function 'ata_scsiop_read_capacity10':
ahci.c:616: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Update fsl_sata to use common structures instead of casting
back and forth between the fsl specific ones and the common ones
(which are identical).
fsl_sata.c: In function 'scan_sata':
fsl_sata.c:550: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:549: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:548: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:545: note: initialized from here
fsl_sata.c:592: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:590: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:588: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:586: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:579: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
...
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch adds a SATA harddisk driver for the canyonlands.
This patch is kernel driver's porting.
This patch corresponded to not cmd_scsi but cmd_sata.
This patch divided an unused member with ifndef __U_BOOT__ in the structure.
[environment variable, boot script]
setenv bootargs root=/dev/sda7 rw
setenv bootargs ${bootargs} console=ttyS0,115200
ext2load sata 0:2 0x400000 /canyonlands/uImage
ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb
fdt addr 0x800000 0x4000
bootm 0x400000 - 0x800000
If you drive SATA-2 disk on Canyonlands, you must change parts from
PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using
following disks:
1.Vendor: Fujitsu Type: MHW2040BS
2.Vendor: Fujitsu Type: MHW2060BK
3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT
4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required)
5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required)
6.Vendor: Hitachi Type: HTS543232L9A300 (CONFIG_LBA48 required)
7.Vendor: Seagate Type: ST31000333AS (CONFIG_LBA48 required)
8.Vendor: Transcend Type: TS32GSSD25S-M
9.Vendor: MTRON Type: MSD-SATA1525-016
Signed-off-by: Kazuaki Ichinohe <kazuichi at fsi.co.jp>
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The curr_device variable really should be namespaced with a "sata_" prefix
since it is only used by the sata code. It also avoids random conflicts
with other pieces of code (like cmd_mmc):
common/libcommon.a(cmd_sata.o):(.data.curr_device+0x0):
multiple definition of `curr_device'
common/libcommon.a(cmd_mmc.o):(.data.curr_device+0x0): first defined here
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Mflash is fusion memory device mainly targeted consumer eletronic and
mobile phone.
Internally, it have nand flash and other hardware logics and supports
some different operation (ATA, IO, XIP) modes.
IO mode is custom mode for the host that doesn't have IDE interface.
(Many mobile targeted SoC doesn't have IDE bus)
This driver support mflash IO mode.
Followings are brief descriptions about IO mode.
1. IO mode based on ATA protocol and uses some custom command. (read
confirm, write confirm)
2. IO mode uses SRAM bus interface.
Signed-off-by: unsik Kim <donari75@gmail.com>
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judging from other printfs in the same file, it seems ata should be
postpended with the interface number, not the address of the global
port variable. Fixes this for current u-boot-mpc83xx tree:
Configuring for MPC8349ITX board...
sata_sil3114.c: In function 'sata_bus_softreset':
sata_sil3114.c:99: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
sata_sil3114.c:108: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The code assumes that the pci bus address and the virtual
address used to access a region are the same, but they might
not be. Fix this assumption.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
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This is a port of the Linux Blackfin on-chip ATAPI driver to U-Boot.
Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The driver need wait for the device updating signature to host.
If we don't wait for it, the driver can not detect the device(disk)
when the system powers up.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Tor Krill <tor@excito.com>
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This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Current libata.h of u-boot is out of sync from linux kernel,
this patch make it be consistent with linux kernel.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Tor Krill <tor@excito.com>
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Signed-off-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Add the Freescale on-chip SATA controller driver to u-boot,
The SATA controller is used on the 837x and 8315 targets,
The driver can be used to load kernel, fs and dtb.
The features list:
- 1.5/3 Gbps link speed
- LBA48, LBA28 support
- DMA and FPDMA support
- Two ports support
Signed-off-by: Dave Liu <daveliu@freescale.com>
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add simple libata support in u-boot
Signed-off-by: Dave Liu <daveliu@freescale.com>
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original ata_piix driver is using IDE framework, not real
SATA framework. For now, the ata_piix driver is only used
by x86 sc520_cdp board. This patch makes the ata_piix driver
use the new SATA framework, so
- remove the duplicated command stuff
- remove the CONFIG_CMD_IDE define in the sc520_cdp.h
- add the CONFIG_CMD_SATA define to sc520_cdp.h
Signed-off-by: Dave Liu <daveliu@freescale.com>
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move the sata.h from include/ to drivers/block/ata_piix.h
Signed-off-by: Dave Liu <daveliu@freescale.com>
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move the cmd_sata.c from common/ to drivers/ata_piix.c,
the cmd_sata.c have some part of ata_piix controller drivers.
consolidate the driver to have better framework.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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