Age | Commit message (Collapse) | Author |
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This adds initial support for the Toradex Aquila AM69 module.
Upstream-Status: Pending
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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The fs-loader driver reads env storage_interface and uses it to load
firmware file into memory using the medium set by env. Update the driver
to use env fw_storage_interface as this variable is only used to load
firmwares. This is to keep all variables used by fs-loader driver with
'fw_' prefix. All other variables have 'fw_' prefix except for
storage_interface.
The env storage_interface will act as fallback so that the
existing implementations do not break.
Also update the FS Loader documentation accordingly.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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commit 09a17b0d01dd7c81f6fd96228581d7df47a1a7b1 upstream
Mention TI_DM argument can be used to fetch a custom DM binary in the
A72 build instructions for K3 devices.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
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RC Release 09.01.00.006
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This commit adds a general flow to explain the usage of firewalls and
the chain of trust in K3 devices.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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RC Release 09.00.00.008
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Binman enablement.
Upstream-Status: Pending
Binman support missing upstream
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
V1.0A module. They are strapped to boot from their on-module eMMC.
U-Boot supports booting from the on-module eMMC only, DFU support is
disabled for now due to missing AM62x USB support.
Boot sequence is:
SYSFW ---> R5 SPL (both in tiboot3.bin) ---> ATF (TF-A) ---> OP-TEE
---> A53 SPL (part of tispl.bin) ---> U-boot proper (u-boot.img)
Upstream-Status: Pending
V2 has been sent [1] and a re-based V3 will be sent once the upstream
TI stuff sufficiently stabilizes.
[1] https://lore.kernel.org/all/20230612205444.363727-4-marcel@ziswiler.com
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Having saved environments usually causes inconsistencies while in
development workflow. The saved environments conflict with the
default ones that U-boot should be updating during development
but that doesn't happen and the saved environments need to be
reset during bootups to test the changes causing extra debugs.
Remove the saved environments as a default. Environments can always
be re-enabled locally if one does like them or needs them for
some production environment. Optionally, Uenv.txt can also be used on
some of the boot media.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Add documentation for signing secondary platforms as a
part of enabling the fit signature signing in u-boot.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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This patch adds documentation for j7200 SOC
Acked-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Judith Mendez <jm@ti.com>
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Update README to add j7200 specific commands and memory layout for eMMC and
OSPI.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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Earlier documentation specified builds for generating bootloader images
using an external TI repository k3-image-gen and core-secdev-k3. Modify
this to using the binman flow so that user understands how to build the
final boot images.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c85b20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf5bfc)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ EMPTY │
├─────────────────────────────────────┤ 0x41c81920
│ STACK │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf59f0)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ 0x41cff9fc
│ NEW MCU SCRATCHPAD │
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[n-francis@ti.com: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
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Now that Linux has accepted these tags, move U-Boot over to use them.
Tidy up the comments and formatting, making sure that VPL is mentioned
too.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Now that Linux has accepted these tags, move U-Boot over to use them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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U-Boot has some particular challenges with device tree and devices:
- U-Boot has multiple build phases, such as a Secondary Program Loader
(SPL) phase which typically runs in a pre-SDRAM environment where code
and data space are limited. In particular, there may not be enough
space for the full device tree blob. U-Boot uses various automated
techniques to reduce the size from perhaps 40KB to 3KB. It is not
always possible to handle these tags entirely at build time, since
U-Boot proper must have the full device tree, even though we do not
want it to process all nodes until after relocation.
- Some U-Boot phases needs to run before the clocks are properly set up,
where the CPU may be running very slowly. Therefore it is important to
bind only those devices which are actually needed in that phase
- U-Boot uses lazy initialisation for its devices, with 'bind' and
'probe' being separate steps. Even if a device is bound, it is not
actually probed until it is used. This is necessary to keep the boot
time reasonable, e.g. to under a second
The phases of U-Boot in order are: TPL, VPL, SPL, U-Boot (first
pre-relocation, then post-relocation). ALl but the last two are optional.
For the above reasons, U-Boot only includes the full device tree in the
final 'U-Boot proper' build. Even then, before relocation U-Boot only
processes nodes which are marked as being needed.
For this to work, U-Boot's driver model[1] provides a way to mark device
tree nodes as applicable for a particular phase. This works by adding a
tag to the node, e.g.:
cru: clock-controller@ff760000 {
bootph-all;
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
...
};
Here the "bootph-all" tag indicates that the node must be present in all
phases, since the clock driver is required.
There has been discussion over the years about whether this could be done
in a property instead, e.g.
options {
bootph-all = <&cru> <&gpio_a> ...;
...
};
Some problems with this:
- we need to be able to merge several such tags from different .dtsi files
since many boards have their own specific requirements
- it is hard to find and cross-reference the affected nodes
- it is more error-prone
- it requires significant tool rework in U-Boot, including fdtgrep and
the build system
- is harder (slower, more code) to process since it involves scanning
another node/property to find out what to do with a particular node
- we don't want to add phandle arguments to the above since we are
referring, e.g., to the clock device as a whole, not a paricular clock
- the of-platdata feature[2], which converts device tree to C for even
more constrained environments, would need to become aware of the
/options node
There is also the question about whether this needs to be U-Boot-specific,
or whether the tags could be generic. From what I can tell, U-Boot is the
only bootloader which seriously attempts to use a runtime device tree in
all cases. For this version, an attempt is made to name the phases in a
generic manner.
It should also be noted that the approach provided here has stood the test
of time, used in U-Boot for 8 years so far.
So add the schema for this. This will allow a major class of schema
exceptions to be dropped from the U-Boot source tree.
This has been applied upstream[3]
[1] https://u-boot.readthedocs.io/en/latest/develop/driver-model/index.html
[2] https://u-boot.readthedocs.io/en/latest/develop/driver-model/of-plat.html
[3] https://github.com/devicetree-org/dt-schema/commit/63bd847
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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commit 354c05f265eb42ef90e5411ddad684f752d0587b upstream.
List some common boot modes and their corresponding switch
settings for AM62 SK.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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commit 3e7b71c7286b8e12891c4fd954c21ed8be018de7 upstream.
Update the Android documentation to describe version 3 and 4 of boot
image header.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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'git push -o ci.skip' can be used to push to Gitlab without triggering a
pipeline.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Add documentation on how to make this change safely.
Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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As explained in the text at the bottom of the page
https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format:
"QUIC repositories on this site will not receive any updates after
March 31, 2022, and will be deleted on March 31, 2023."
Point to the NXP boot format github repo instead.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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Provide a man-page for the panic command.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Fix a couple of links so that they are rendered correctly with sphinx.
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
Boot log for the record,
DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO: Preloader serial: 2
NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE: BL31: Built : 14:15:50, Jul 18 2022
INFO: ext 32k is not valid
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: system boots from cpu-hwid-0
INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO: BL31: Initialising Exception Handling Framework
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0xa00000
INFO: SPSR = 0x3c9
U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Model: Edgeble Neu6A IO Board
DRAM: 7.5 GiB (effective 3.7 GiB)
Core: 71 devices, 15 uclasses, devicetree: separate
MMC: mmc@fe2c0000: 0
Loading Environment from nowhere... OK
In: serial@feb50000
Out: serial@feb50000
Err: serial@feb50000
Model: Edgeble Neu6A IO Board
Net: No ethernet found.
Hit any key to stop autoboot: 0
=>
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.
Also update Rockchip board docs to include information on building
RK3568 based devices.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.
However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.
Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
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We have been using Sphinx >=3 since 2020. We don't expect issues.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Move board/gateworks/venice/README to RST documentation.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Fix typo and whitespace in the document.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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fifo-depth
Add description for fifo-depth parameter that can be used
in the device tree.
Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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Revamp the documentation for the new features, including a description of
the new features and documentation for the trace command.
Signed-off-by: Simon Glass <sjg@chromium.org>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-04-rc2
Documentation:
* Provide page with links to talks on U-Boot
UEFI:
* Enable CTRL+S to save the boot order in eficonfig command
* Run attribute check for QueryVariableInfo() only for the file store
* Bug fixes
Others:
* Improve output formatting of the coninfo command
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 10 Feb 2023 12:15:45 PM EST
# gpg: using RSA key 6DC4F9C71F29A6FA06B76D33C481DBBC2C051AC4
# gpg: Good signature from "Heinrich Schuchardt <xypron.glpk@gmx.de>" [unknown]
# gpg: aka "[jpeg image of size 1389]" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4
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Remove ns16550 configuration from header files. Document
DM_SERIAL-required prior stage device tree configuration.
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On the sandbox called without "--terminal raw" CTRL+C leaves U-Boot,
"ESC/CTRL+C to quit" is misleading.
Let's remove CTRL+C to quit key handling from bootmenu and eficonfig menu.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Talks are a great way to learn about U-Boot and have been lost now that
the Denx Wiki has gone away.
These are stored at elinux.org so link to that .
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
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Add missing information to the configuration section of the setexpr
man-page.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add a command to load SEAMA (Seattle Image), a NAND flash
on-flash storage format.
This type of flash image is found in some D-Link routers such
as DIR-645, DIR-842, DIR-859, DIR-860L, DIR-885L, DIR890L and
DCH-M225, as well as in WD and NEC routers on the ath79
(MIPS), Broadcom BCM53xx, and RAMIPS platforms.
This U-Boot command will read and decode a SEAMA image from
raw NAND flash on any platform. As it is always using big endian
format for the data decoding is always necessary on platforms
such as ARM.
The command is needed to read a SEAMA-encoded boot image on the
D-Link DIR-890L router for boot from NAND flash in an upcoming
port of U-Boot to the Broadcom Northstar (BCM4709, BCM53xx)
architecture.
A basic test and documentation is added as well. The test must
be run on a target with NAND flash support and at least one
resident SEAMA image in flash.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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We need to support a basic set of filesystems for booting to work in most
cases. Add these in via a new option, letting the board disable them
individually (for space reasons) if desired.
This enables the filesystem commands as well as the actual functionality,
even though bootstd is quite happy to use ext4 without the ext4 command.
Further work would be needed to disintangle this and reduce code size.
Add several other options as well, providing sensible defaults.
We cannot enable this by default, since it expands the size of many
boards quite a lot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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