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Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd to prevent us from trying to access
non-mapped memory.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.
Signed-off-by: Stefan Roese <sr@denx.de>
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- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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This patch simplifies post_word_{load,store} by using the preprocessor
to eliminate redundant, copy-and-pasted code.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
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This adds a driver for the SPI controller found on most AT91 and AVR32
chips, implementing the new SPI API.
Changed in v4:
- Update to new API
- Handle zero-length transfers appropriately. The user may send a
zero-length SPI transfer with SPI_XFER_END set in order to
deactivate the chip select after a series of transfers with chip
select active. This is useful e.g. when polling the status
register of DataFlash.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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This patch gets rid of the spi_chipsel table and adds a handful of new
functions that makes the SPI layer cleaner and more flexible.
Instead of the spi_chipsel table, each board that wants to use SPI
gets to implement three hooks:
* spi_cs_activate(): Activates the chipselect for a given slave
* spi_cs_deactivate(): Deactivates the chipselect for a given slave
* spi_cs_is_valid(): Determines if the given bus/chipselect
combination can be activated.
Not all drivers may need those extra functions however. If that's the
case, the board code may just leave them out (assuming they know what
the driver needs) or rely on the linker to strip them out (assuming
--gc-sections is being used.)
To set up communication parameters for a given slave, the driver needs
to call spi_setup_slave(). This returns a pointer to an opaque
spi_slave struct which must be passed as a parameter to subsequent SPI
calls. This struct can be freed by calling spi_free_slave(), but most
driver probably don't want to do this.
Before starting one or more SPI transfers, the driver must call
spi_claim_bus() to gain exclusive access to the SPI bus and initialize
the hardware. When all transfers are done, the driver must call
spi_release_bus() to make the bus available to others, and possibly
shut down the SPI controller hardware.
spi_xfer() behaves mostly the same as before, but it now takes a
spi_slave parameter instead of a spi_chipsel function pointer. It also
got a new parameter, flags, which is used to specify chip select
behaviour. This may be extended with other flags in the future.
This patch has been build-tested on all powerpc and arm boards
involved. I have not tested NIOS since I don't have a toolchain for it
installed, so I expect some breakage there even though I've tried
fixing up everything I could find by visual inspection.
I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and
DataFlash drivers posted as a follow-up. I'd like some help testing
other boards that use the existing SPI API.
But most of all, I'd like some comments on the new API. Is this stuff
usable for everyone? If not, why?
Changed in v4:
- Build fixes for various boards, drivers and commands
- Provide common struct spi_slave definition that can be extended by
drivers
- Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate
- Make default bus and mode build-time configurable
- Override default SPI bus ID and mode on mx32ads and imx31_litekit.
Changed in v3:
- Add opaque struct spi_slave for controller-specific data associated
with a slave.
- Add spi_claim_bus() and spi_release_bus()
- Add spi_free_slave()
- spi_setup() is now called spi_setup_slave() and returns a
struct spi_slave
- soft_spi now supports four SPI modes (CPOL|CPHA)
- Add bus parameter to spi_setup_slave()
- Convert the new i.MX32 SPI driver
- Convert the new MC13783 RTC driver
Changed in v2:
- Convert the mpc8xxx_spi driver and the mpc8349emds board to the
new API.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Tested-by: Guennadi Liakhovetski <lg@denx.de>
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Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.
This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:
csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG
I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch makes the common 4xx ECC code really usable on 440GP style
platforms.
Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
we need to make some processor dependant defines used later on by the
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).
It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:
used on 405GR/CR/EP and some Xilinx Virtex boards.
used on 440GP/GX/EP/GR.
used on 440EPx/GRx.
used on 405EX/r/440SP/SPe/460EX/GT.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.
Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
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This patch (Part 1 of 2):
* Rolls up a suite of changes to enable correct primordial stack and
global data handling when the data cache is used for such a purpose
for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by
eliminating redundant ECC initialization implementations and moving
redundant SDRAM initialization out of board code into shared 4xx
code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on
both AMCC's Kilauea and Makalu and removes a redundant
CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.
With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch simplifies post_word_{load,store} by using the preprocessor
to eliminate redundant, copy-and-pasted code.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
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Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now. Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
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If the specified delay is very short, the cycle counter may go past the
"end" time we are waiting for before we get around to reading it.
Fix it by checking the different between the cycle count "now" and the
cycle count at the beginning. This will work as long as the delay
measured in number of cycles is below 2^31.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Remove #ifdef CONFIG_MMC from the source file and use conditional
compilation in the Makefile instead.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Make sure we check for CRC errors when sending commands that use CRC
checking.
Reported-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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The warnings are harmless but annoying. Let's fix them.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.
* Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
* Remove memory test from sdram_init() and make caller responsible
for verifying the SDRAM and determining its size.
* Remove base_address member from struct sdram_config (was sdram_info)
* Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
* Add support for a common STK1000 hack: 16MB SDRAM instead of 8.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Don't do a stack dump if the stack pointer is outside the memory area
reserved for stack.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Since the reset vector is always aligned to a very large boundary, we
can save a couple of KB worth of alignment padding by placing the
exception vectors at the same address.
Deciding which one it is is easy: If we're handling an exception, the
CPU is in Exception mode. If we're starting up after reset, the CPU is
in Supervisor mode. So this adds a very minimal overhead to the reset
path (only executed once) and the exception handling path (normally
never executed at all.)
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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pm_init() was always more about clock initialization than anything
else. Dealing with PLLs, clock gating and such is also inherently
SoC-specific, so move it into a SoC-specific directory.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This makes it easier to avoid compiling certain files later.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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The .flashprog section was only needed back when we were running
directly from flash, and it's even more useless on NGW100 since it
uses the CFI flash driver which never used this workaround in the
first place.
Remove it on STK1000 as well, and get rid of all the associated code and
annotations.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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This patch forces the watchdog off in all cases. That will at least
get rid of the constant reboot cycle, though it won't let the watchdog
actually run in the new kernels: its probe() comes up with a polite
warning.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Merge branch 'testing-V2'
Conflicts:
board/atmel/at91cap9adk/Makefile
Fixing copyright
board/atmel/at91sam9260ek/Makefile
Fixing copyright
board/atmel/at91sam9260ek/u-boot.lds
Delete no more needed ld script
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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introduced by 53677ef18 "Big white-space cleanup."
Signed-off-by: Wolfgang Denk <wd@denx.de>
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This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds support for the AT91SAM9261 chip and the AT91SAM9261EK
board.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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All the AT91CAP9/AT91SAM9 boards have the same linker script. The patch
below avoids the duplication of u-boot.lds by putting the file in the
cpu directory instead of the board one.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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When applying the AT91CAP9 patches upstream, something transformed
the '@' character into the ' <at> ' sequence.
The patch below restores the original form in all the places where
it has been modified (the AT91CAP9 files, the AT91SAM9260 files which
were copied from AT91CAP9, and a couple of other files where the
' <at> ' sequence was present).
Signed-off-by: Stelian Pop <stelian@popies.net>
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According to schematics and to RedBoot sources, the MX31ADS uses a 32768Hz
oscillator as a SKIL source. Fix previously wrongly assumed 32000Hz value.
Also fix a typo when verifying a jumper configuration. While at it, make
two needlessly global functions static.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
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This patch fixes three typos.
The first is a repetition of CONFIG_CMD_BSP.
The second makes the #endif comment match its #if.
The third is a spelling error.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
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The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.
This patch addresses both of these bugs.
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Acked-By: Jon Loeliger <jdl@freescale.com>
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When applying the AT91CAP9 patches upstream, something transformed
the '@' character into the ' <at> ' sequence.
The patch below restores the original form in all the places where
it has been modified (the AT91CAP9 files, the AT91SAM9260 files which
were copied from AT91CAP9, and a couple of other files where the
' <at> ' sequence was present).
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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