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Switch options for NAND boot are SW[1:4]='0101"
To Boot from NAND
1. tftp 1000000 u-boot-nand.bin
2. nand erase 0 80000
3. nand write 1000000 0 80000
4. Change the Switch settings to boot from NAND.
5. reset the board.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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RAMBOOT support over SDCARD boot
RAMBOOT support to run uboot on uboot prompt itself,
Usage is,
tftp 0x11000000
go 11000000
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Define CONFIG_FSL_ESDHC for eSDHC clk
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Fixup SDHC clock-frequency in dts.
This Patch is borrowed from MPC8536DS.
The clock-frequency of SD controller come from different source
on different platform. We add a clock-frequency property in the
dts and set the value in u-boot.
Signed-off-by: Gao Guanhua <B22826@freescale.com>
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Make a special uboot used for booting from SDcard or SPI flash
This Patch is borrowed from MPC8536DS SD Card Boot.
This patch is used to generate a special version u-boot,
together with the data structure on the SDcard/SPI flash,
can be used to booting from SDcard/SPI flash on 8536DS board.
The boot ROM in CPU and the data structure on SD card will initialize
the DDR, set a large tlb0 for DDR and CCSR, set law0 for DDR. The special
version uboot avoid initializing the DDR. Try to reseve the law0 for DDR
by adding a CONFIG_SYS_RESERVED_LAW0 macro for the "dynamic law allocation"
code. But keep the original tlb initialize code for DDR, disabled the large
tlb0 which was set in the boot ROM.
This patch is intend for those who are interested in the function of
booting from SD card on 8536DS board and not for opensource.
An utility is needed to write the data structure and the special
version u-boot onto the SD card which has filesystem on it or onto
the SPI flash.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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Adds support for P20x0 processors of QorIQ series.
The processors are Low end and Ultra Low End products in QorIQ series.
All are e500 based with small variations.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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DDR data width getting detected dynamically based on SVR value.
Would be helpful to cater more than one similar platforms with a single u-boot image.
(for example, P1020(32 bit DDR), P2020(64 bit DDR))
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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Removed CONFIG_NUM_CPUS for 85xx processor series.
Instead the num of cores is determined dynamically by reading the SVR values.
This can help to use the same u-boot image across the platforms.
Added CONFIG_MAX_CPUS value 8.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.
Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
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Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select.
To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new
define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by
Total5200 and will be used by digsy MTC and other boards with
ATA CS on I2C pins.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
is not enabled before code runs from RAM.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Update PLATFORM_CPPFLAGS to accept 4.3.x version of
ColdFire compiler.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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The serial boot dram extended/standard mode register was not
setup and was using default DRAM setup causing the U-boot was
unstable to boot up in serial mode.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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According to coldfire manual data timeout > address time out
also use correct macro to program XARB_CFG
Signed-off-by: Arun C <arunedarath@mistralsolutions.com>
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The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Read and store OMAP3 die ID in U-Boot environment.
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
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Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Conflicts:
lib_ppc/board.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.
The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.
This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
items 1, 2 and 5:
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Fixes commit 407976185e0dda2c90e89027121a1071b9c77bfb
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
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We should use pci_last_busno() in pci_init_bus(), otherwise we'll
erroneously re-use PCI0's first_busno for PCI1 hoses.
NOTE: The patch is untested. All MPC83xx FSL boards I have have
PCI1 in miniPCI form, for which I don't have any cards handy.
But looking in cpu/mpc85xx/pci.c:
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#ifdef CONFIG_MPC85XX_PCI2
hose = &pci_hose[1];
hose->first_busno = pci_hose[0].last_busno + 1;
And considering that we do the same for MPC83xx PCI-E support,
I think this patch is correct.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch fixes copy-paste issue: pci_hose[0]'s first and last
busnos were used to fixup pci1's nodes.
We don't see this bug triggering only because Linux reenumerate
buses anyway.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch fixes an issue in config space read accessors: we should
fill-in the value even if we fail (e.g. skipping devices), otherwise
CONFIG_PCI_SCAN_SHOW reports bogus values during boot up.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Currently we assign first_busno = 0 for the first PCIe hose, but this
scheme won't work if we have ordinary PCI hose already registered (its
first_busno value is 0 too).
The old code worked fine only because we have PCI disabled on
MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92e3b13f2b3
"mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards").
But on MPC837XERDB boards we have PCI and PCIe, so the bug actually
triggers.
So, to fix the issue, we should use pci_last_busno() + 1 for the
first_busno (i.e. last available busno).
Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch adds OMAP3 cpu type auto detection based on OMAP3 register
and removes hardcoded values.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
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Looks like the initcode updates fell out of order during my merges. The
patch that really fixes up this code is part of power-on overhaul and so
is too large for merging at this point. Instead, we can disable the code
as no currently in-tree board depends on it. The next merge window will
fix things up properly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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In the commit 79b51ff8205f0354d5300570614c1d2db499679c ([MIPS] cpu/mips/
Makefile: Split [CS]OBJS onto separate lines), I wrongly deleted a START
line. This patch puts it back.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
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introduce new macro CONFIG_PXA_MMC to activate it
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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These structures are defined in the common mmc.h
This was compile checked on cerf250.
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Fixing the get_timer function to return time in miliseconds instead of
ticks. Also fixed PXA boards to use the conventional value of 1000 for
CONFIG_SYS_HZ.
Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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This patch fixes a problem recently seen on some 4xx platforms. For
example on Kilauea PCIe slot #0.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Andy Fleming <afleming@freescale.com>
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The current MMC infrastructure relies on the existence of an
arch-specific header file. This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This is to get it out of the way of incoming MMC framework
Signed-off-by: Andy Fleming <afleming@freescale.com>
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MMC cards are not memory, so we stop treating them that way.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This errata fix is required for 32 bit DDR2 controller on 8572.
May also be required for P10XX20XX platforms
Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
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- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
== Before ==
Freescale PowerPC
CPU:
Core: E600 Core 0, Version: 0.2, (0x80040202)
System: Unknown, Version: 2.1, (0x80900121)
Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC
== After ==
CPU: 8641D, Version: 2.1, (0x80900121)
Core: E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1066.667 MHz, MPX:533.333 MHz
DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1: D-cache 32 KB enabled
I-cache 32 KB enabled
L2: 512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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