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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This issue due to PODF is not used correcly, need use the following instead:
ACLK_EMI_SLOW_PODF_OFFSET, the original used ACLK_EMI_PODF_OFFSET was wrong.
Signed-off-by: Jason Liu <r64343@freescale.com>
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move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove
CONFIG_MX6_INTER_LDO_BYPASS in u-boot
Signed-off-by: Robin Gong <b38343@freescale.com>
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* Adding the config option CONFIG_SECURE_BOOT to the SabreSD board,
but defaulting it to be disabled. Removed the CONFIG_SECURE_BOOT
key from mx6q_arm2_android.h so that it is only in one file,
include/configs/mx6q_arm2.h
* Fixed up an address alignment check in authenticate_image(). The
test would fail in the event the address is already aligned.
Also, added some debug code which can be enabled to assist in
testing secure images.
* Added support for authenticating an image when using booti.
* Adding support for secure boot to the Sabre SD board.
* Added support for encrypted boot to mx6q arm2 board linker script.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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We need to check reg bit to decide I2C parent clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Disable VDDPU_CAP by default, xPU will enable it
in driver when they need it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch changes to keep IPU display channel being running
rather than disable IPU display channel when we leave uboot
stage and go to kernel stage. This may support smooth
tranistion from Uboot splash screen to kernel stage.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Previous temperature range is -25C ~ 125C, according to latest
datasheet, change it to -40C to 125C.
Fix temperature report error when it is < 0C.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add cpu serial number tag, kernel will read this
number and put it in /proc/cpuinfo, as 'Serial' part
it can be used as a UUID source in software.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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The original secure boot implementation make a consumption that
u-boot.bin will not exceed 0x2F000. With this consumption, the hab data
is hard coded in linker script file to relative address 0x2F000 without
causing any problem.
But when this consumption don't hold, the hard coded way will cause
memory region overlap and break build. So we need to change to a dynamic
way of allocating hab_data. The new implementation put hab data at the
next 0x1000 alignment after u-boot data and text section, instead of
hard coded to 0x2F000.
Similar changes is made to uImage authentication implementation.
Changes in U-Boot includes:
- in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000
- change authenticate_image implementation, originally the uImage
parameters are hard coded, now they are retrived from the
"load_addr" and the image_hdr
The new secure image layout:
U-Boot
+-------------------+ DDR_START
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| U-Boot Image |
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+-------------------+ DDR_START + UBOOT_SIZE
| PADDING |
+-------------------+ align to 0x1000
| CSF Data | -
+-------------------+ +-- CSF + Pad, Size : 0x2000
| PADDING | -
+-------------------+
uImage
+-------------------+ DDR_START
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| uImage |
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+-------------------+ DDR_START + UIMAGE_SIZE
| PADDING |
+-------------------+ align to 0x1000
| IVT | ---- Size : 0x20
+-------------------+
| CSF Data | -
+-------------------+ +-- CSF + Pad, Size : 0x2000
| PADDING | -
+-------------------+
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Fix the build warning in uboot build.
Fix bug of incorrect dereference to periph2 clock pre divider.
Fix incorrect type of maxpackage size assign, even it's
not used at all in fastboot.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Move the secure boot related implementation code from mx6q_arm2.c to
mx6/generic.c. In this way the HAB feature can be shared by all MX6
platforms
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Fix the PAD_LVE implementation used on MX6SL.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
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- move recovery.h to common inlcude place.
- move supported_reco_envs to soc related, not board related,
- user can change this via configure header,
don't needs this in every board file.
- pass build for all mx5/mx6 android configs.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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cleanup android fastboot and udc build warnnings.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Original pad configuration don't provide enough bitfield width to hold
all necessary information. For MX6Sololite, a "PAD_CTL_LVE" is needed
to be configed for many pins.
iomux_v3_cfg_t is re-orgnized to address this issue. PAD_CTRL is
extended by 1 bit to hold the "PAD_CTL_LVE". Which is mapped to proper
bit location when configure the PAD config register.
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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1. add check asrc register to enter recovery mode,
rather then check the file.
2. fix the boot.img can not fastboot flash function.
3. consolidate and cleanup fastboot code.
4. clean up many build warnning message.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This patch is to add the initial support for Freescale i.mx6sl chip.
i.mx6sl is the SoloLite verison of Freescale i.mx6 family.
The patch does:
- memory layout support,
- iomux support,
- clock support,
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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add fastboot function back in MX6Q_SABERSD board.
the MX6DL_SABERSD have usb init related issue which will
keep RESET, but left as later developement.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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For example: The soc rev on i.mx6dl rev 1.0 not print correctly:
CPU: Freescale i.MX 6 family 0.0V at 792 MHz
This patch help u-boot print out the SOC revision correctly:
CPU: Freescale i.MX6 family TO1.0 at 792 MHz
Signed-off-by: Jason Liu <r64343@freescale.com>
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Remove build warnings for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add CONFIG_MXC_FEC macro to fec init code.
Add CONFIG_VIDEO_MX5 to ipu init code.
Change temperature function as static.
For in iram boot, FEC configs is not needed, those FEC init code will
cause build errors.
These changes can reduce image size.
Signed-off-by: Terry Lv <r65388@freescale.com>
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PCIe is power on by defaultt, we need to power down
it in u-boot, it can save more than 1mW during suspend.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The root cause is the L1 I-cache need invalidation,
now we don't need this workaround, so remove it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Disable the uboot workaround. It will crash the MFGTOOL.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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We need to check CPU temperature in uboot, if cpu
is too hot, we will let it waiting there until cpu
temperature drop to save region, then go on boot
up.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix incorrect VDDSOC voltage setting in uboot.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add workaround for POR/wdog reset issue, we need to
do a CORE LDO reset everytime POR/wdog reset, otherwise
kernel will crash or hang when we booting more than 2
cores. Root cause is still under investigation, it is
analog/power related issue, may take long time to
identify the root cause, we need to add workaround to make
function ready first. The flow of workaround is as below:
1. Check CORE LDO reset flag, currently stored in SNVS_LPGPR[0];
2. If it is there, clear it, go on boot up system; If not,
Set the flag, configure wdog to timeout in 0.5 seconds, then
disable CORE LDO and wait for wdog timeout;
This workaround will bring 0.5~1 seconds delay of booting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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add support for otg in MX6Q uboot to enable fastboot function.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add "download_mode" command to U-Boot. It will force a system reset and let
boot running in "boot from serial rom" mode, which can be used by manufacturing
tool.
The command will triggle a write to SRC_GPR9 and SRC_GPR10, then triggle a
watchdog reset. GPR9 and GPR10 can maintain their value during the reset, the
value in it make ROM to start in "boot from serial rom" mode. After that GPR9
and GPR10 are written by their original value for normal boot.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Add download_mode command in uboot to enter MFG dowload mode ,
you can try download mode command in uboot and enter download mode.
it first set srtc register, then before enter linux,
it will clear these register to prevent the up comming watchdog
reset will enter mfgtool mode.
only add mx53 now.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add enet clk change support for mx6.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Set the VDDSOC LDO to increase the VDDSOC cap to 1.2V.
This is required for correct functioning of GPU and when the
ARM LDO is set to 1.225V (when ARM core is at 1GHz).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Move the code to read the mac address from the fuse to SoC file
and out of the board file
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add iomux and clock setting in Uboot code to support NAND, due to
the conflict between NAND and SD, NAND function is not enabled in
default configuration.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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1. add force option to blow operation
2. add blown value check
3. add simple validation for zeros returned by 'simple_strtoul' call
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Only support LVDS0 splash screen.
Enable splash process:
1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h
2.Config U-boot with followed command:()
setenv splashimage '0x30000000'
#Set splash position as Center
setenv splashpos 'm,m'
#Set LVDS via LVDS bridge 0
setenv lvds_num 0
Signed-off-by: Sandor Yu <r01008@freescale.com>
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1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz.
2. When dpgdck0_2_en is 0, the formula to calculate output freq
will be changed to 2 * freq * [].
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. ENET don't need to enable ENET pll clock;
2. Enable cpu debug clock in case of using JTAG;
3. Clean up some debug info during bring up.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch is used to support watchdog timeout in SMD RevA, RevB
board.
1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the
board".
2. Force warm reset as cold reset.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Use 528M DDR script
Disable L2 cache because rom enable L2 cache when use plug-in
Fix usdhc pad settings
Remove mac address hardcode
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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For clk command always make console output mess characters,
here we reinitilize it after clock is changed.
Signed-off-by: Terry Lv <r65388@freescale.com>
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In mx53 smd, to type "reset" command in u-boot console can
not reset the system. It hangs in ROM with unknown reason.
This patch adds one workaround to configure GPIO_9 (WDT_OUTPUT_B)
as GPIO and pull down it to reset DA9053 PMIC.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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mx50 reboot fail when booting from spi nor.
Reconfigure eCSPI SS signal as GPIO before reset.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add perclk_lp_apm_sel check to function __get_ipg_per_clk.
This will get more accute clock frequency.
Signed-off-by: Terry Lv <r65388@freescale.com>
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We're following the following rules:
1. FSL copyright should be added for freescale added and modified files.
2. FSL copyright should go after existing copyrights.
3. For Duplicate FSL copyright, Our copyright will go after that also.
4. FSL copyright should not include personal names as part.
5. For only FSL copyright, "All rights reserved" is not mattered.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Enable fastboot support for mx50 rdp.
Signed-off-by: Sammy He <r62914@freescale.com>
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As now mx51 DDR frequency is derived from PLL1.
We need to get DDR frequency from PLL1.
Mx53 don't use PLL1 for ddr clock source,
so just the precision is adjusted.
Mx50 don't support clk command yet.
DDR config function is modified according to
mx50 spec, but not tested yet.
Signed-off-by: Terry <r65388@freescale.com>
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This patch fixes the kernel bootup random hang issue by disabling
DP/DC/DI/IDMAC before we go to kernel. This is a workaround.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch adds ipu base address and ipu clock.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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