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2012-01-05tegra: Tidy up LCD init code to use a state machineSimon Glass
The LCD init takes place over five stages. We want to hide this init behind other operations, so turn it into a state machine which we can call at any time. For now, call it in lcd_enable(). BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Ia0b50ec74108ac4e015de12b7a9628426ea17656 Reviewed-on: https://gerrit.chromium.org/gerrit/13211 Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-03CHROMIUMOS: Issue SMI to finalize Coreboot in final stageDuncan Laurie
This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. BUG=chrome-os-partner:6609 TEST=boot on stumpy+celeron and lumpy+i5 and ensure the system still boots and that registers are locked Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ib30ea83044f5123205531a5e8ee88ee37de2dd86 Reviewed-on: https://gerrit.chromium.org/gerrit/13604 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-03CHROMIUMOS: Add U-boot support for wear-leveling the MRC dataDuncan Laurie
- Depends on related Coreboot changes - There is a 64k region allocated so use it all - Write each data blob in a 4K aligned container - Find the last entry in the region to compare against coreboot copy - Detect a full region and erase it all and start over at zero BUG=chrome-os-partner:6962 TEST=manual I started writing an autotest for this, but it was taking more time than just doing a thorough manual test. I will finish the autotest but for now I relied on manual testing and using /sys/firmware/log to tell what happened in Coreboot/U-boot on each boot. TEST CASE 1 - newly flashed image: 1) Install the new bios with flashrom and reboot 2) Check that no MRC data was found by Coreboot in firmware log: "prepare_mrc_cache: invalid MRC data" 3) Check that U-boot wrote training data in firmware log: "handle_mrc_cache: cached storage mismatch (-1/2895)" "firmware_storage_spi: before adjustment" "firmware_storage_spi: offset: 0x1ec000" "firmware_storage_spi: length: 0xb58" "firmware_storage_spi: after adjustment" "firmware_storage_spi: offset: 0x1ec000" "firmware_storage_spi: length: 0x1000" "firmware_storage_spi: offset: 0x001ec000" "firmware_storage_spi: adjusted offset: 0x001ec000" 4) Check the flash to see if it has data in first slot > flashrom -r /tmp/bios.now > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now TEST CASE 2 - ensure that it uses the saved training data: 1) Reboot 2) Check that Coreboot used the training data in firmware log: "prepare_mrc_cache: at ff9ec009, entry 0 size b4f checksum 9c" 3) Check that U-boot did not have to update the data in firmware log: "handle_mrc_cache: cached storage match" 4) Check the flash to see if it still only has data in first slot: > flashrom -r /tmp/bios.now > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now TEST CASE 3 - ensure that it fills the next slot with new data: 1) Corrupt the seed checksum in CMOS: > io_write8 0x70 0x78 > io_write8 0x71 0x00 2) Reboot 3) Check that Coreboot did not use cached data in firmware log: "prepare_mrc_cache: invalid seed checksum" 4) Check that U-boot wrote new training data at new offset in firmware log: "handle_mrc_cache: cached storage mismatch (2895/2895)" "firmware_storage_spi: before adjustment" "firmware_storage_spi: offset: 0x1ed000" "firmware_storage_spi: length: 0xb58" "firmware_storage_spi: after adjustment" "firmware_storage_spi: offset: 0x1ed000" "firmware_storage_spi: length: 0x1000" "firmware_storage_spi: offset: 0x001ed000" "firmware_storage_spi: adjusted offset: 0x001ed000" Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifffce29c5f9324f110c047a44a3f66d2e21cd6a4 Reviewed-on: https://gerrit.chromium.org/gerrit/13589 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
2011-12-31CHROMIUMOS: x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie
Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. BUG=chrome-os-partner:7350 TEST=boot 4GB stumpy with coreboot MTRR fixes and verify that U-boot does not clear MTRR 7 but does clear MTRR 9. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id6927325131b0b88043daa320a17847764626c0d Reviewed-on: https://gerrit.chromium.org/gerrit/13477 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-21tegra: Implement CONFIG_DELAY_CONSOLESimon Glass
Add plumbing to support this option to delay console init until after relocation. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Iee3be9e2d0b51e6cf2f45a4408bfdde494c97d8b Reviewed-on: https://gerrit.chromium.org/gerrit/13210 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-21tegra: Refactor serial init codeSimon Glass
Move the serial init code into its own function to collect this all in one place. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I70162d836fddfabedd9cfbc07d8f0dc920602af8 Reviewed-on: https://gerrit.chromium.org/gerrit/13204 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20CHROMIUM: config: Switch Kaen to 8-bit eMMCSimon Glass
We can support 8-bit eMMC and it is faster, so turn it on. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I1509594832d317a086fa066d1a37c78a1a52c7c3 Reviewed-on: https://gerrit.chromium.org/gerrit/13201 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20tegra: mmc: Support 8-bit wide interface for eMMCSimon Glass
The Tegra2 can support this faster interface, so use it. It can reduce data transfer time by about 40%. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I656773c83083cd53d3ee52433e324e73fbcdc999 Reviewed-on: https://gerrit.chromium.org/gerrit/13200 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-19tegra: Skip NAND init if fdt indicates it is not activeSimon Glass
This allows NAND to be disabled from the fdt easily. BUG=chromium-os:22938 TEST=build and boot on Kaen Signed-off-by: Fred Signed-off-by: John Change-Id: Ibf9259f8621e73fcf943f54a20327513288fef06 Reviewed-on: https://gerrit.chromium.org/gerrit/12913 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-16Add beep for x86 chormeos.Dylan Reid
Implement the VbExBeep function so that the DEV screen can beep. Much of this code was coppied from coreboot. BUG=chrome-os-partner:7114 TEST=manual, check that Stumpy beeps on DEV screen timeout and when booting from USB with dev_boot_usb=0. Change-Id: Icd4eabb0b10cc3d226db71e6a2b52d3ed7eb25ef Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/13110 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-16x86: Move RO VPD to H2C's positionStefan Reinauer
BUG=chrome-os-partner:7185 TEST=emerge-* chromeos-u-boot chromeos-coreboot chromeos-bootimage Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5361c9ba9519dd726adf9e91747fe08b5e79e9a7 Reviewed-on: https://gerrit.chromium.org/gerrit/13106 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-12-15[x86] FMAP: Move RW_VPD section and add RW_SHARED section backStefan Reinauer
This patch moves the RW VPD section to the same place they live at H2O and H2C for Stumpy and Lumpy, so we can preserve them more easily when switching back and forth. Also, add a RW shared section around the MRC cache and dev cfg, so they get wiped by a recovery firmware update. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:7185 TEST=boot tested on Stumpy Change-Id: I77778d17835b1fe4771370a3523b21c9e5a6b0a7 Reviewed-on: https://gerrit.chromium.org/gerrit/12990 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-12-14fdt: Tegra3: Add Cardhu device-tree fileTom Warren
BUG=chromium-os:23496 TEST=none Modeled on tegra3-waluigi.dts Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I3a31084fa747991484dda4a40e89deda97a1ff1f Reviewed-on: https://gerrit.chromium.org/gerrit/12939 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-14Move RW section of on Sandybridge to lower 4MB of the flash chipStefan Reinauer
H2C splits the flash device in 2 equal partitions of 4MB each. In order to avoid having to adapt user space tools to coreboot, change the flash map on Sandybridge to have the following flash layout: 1.5MB SI_ (ME) sections 2.5MB RW sections 4.0MB RO sections BUG=none TEST=boot tested on Stumpy Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ida0864389644b07b2d284770be62447547fdfb2e Reviewed-on: https://gerrit.chromium.org/gerrit/12937 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-13tegra3: USB: Add/enable USB support in board initTom Warren
BUG=chromium-os:23496 TEST=built Seaboard and Waluigi OK Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I00f6cde99ec4473da3d571fffb1e4adde7828822 Reviewed-on: https://gerrit.chromium.org/gerrit/12443
2011-12-13tegra3: fdt: Add USB fields to T30 Waluigi .dtsTom Warren
BUG=chromium-os:23496 TEST=built Seaboard and Waluigi OK Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I40147ab6d07cc13ef255736f0ebdabe34f85addf Reviewed-on: https://gerrit.chromium.org/gerrit/12441 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-13tegra3: fdt: Add USB to T30 .dtsiTom Warren
BUG=chromium-os:23496 TEST=built Seaboard and Waluigi OK Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I918a326749272032a682dea7c27d86494da31a6f Reviewed-on: https://gerrit.chromium.org/gerrit/12440 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-09reorganize x86 fmapsStefan Reinauer
- obsolete alex fmap is not updated. - drop unused shared-section, ro-recovery, ro-data - make coreboot CBFS 1MB - make GBB 512KB - align RW-A and RW-B to 1MB - increase rw-mrc-cache to 64KB for RW level wearing BUG=chrome-os-partner:7172 TEST=boot coreboot on Stumpy and see it still booting Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4da3b6bf1023bacadaa9b2e07eb07500247e120c Reviewed-on: https://gerrit.chromium.org/gerrit/12704 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-12-08Update 8MB flashmap layout to match new flash descriptor settings.Duncan Laurie
- SI_ME size is now 1.5MB (down from 2MB) - SI_BIOS size is now 6.5MB (up from 6MB) - coreboot-extra region increases by 512K to consume the new space BUG=chrome-os-partner:7147 TEST=boot on stumpy and lumpy with updated descriptor and ME Change-Id: I77e720e453901f9dcfe861e4c41447bf9832f919 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/12654 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2011-12-08fdt: enable USB keyboard on StumpyVincent Palatin
detect keypress at startup on the USB keyboard since we have no internal keyboard. BUG=chrome-os-partner:5752 TEST=on Stumpy, check Ctrl+U, Ctrl+D and space are working as expected in dev mode. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Change-Id: I34762f528817ffd29fa5a1198473f030887990bd Reviewed-on: https://gerrit.chromium.org/gerrit/12583 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2011-12-08add USB keyboard support for vboot.Vincent Palatin
If the primary input of the device is a USB keyboard (as defined by the FDT) and we are in developer mode, enumerate the USB devices at startup and get key strokes from USB keyboard. The keyboard reading is not working correctly yet on the recovery path due to the USB mass storage polling code doing continuous re-enumeration on the USB controller. BUG=chrome-os-partner:5752 TEST=tested on Stumpy and Lumpy, with and without usb-keyboard set in the device tree, check Ctrl+U, Ctrl+D and space are working as expected. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Change-Id: Ib46d6086ae5e5ce631d5f91b467f7b2bf90644d0 Reviewed-on: https://gerrit.chromium.org/gerrit/12543 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-08Modify device tree files for LinkVadim Bendebury
The flash map needs to be reshuffled because the Ivy Bridge MRC does not fit into the room Sandy bridge MRC used to fit in (512K are required instead of 256K), so the entire boot stub gets now 1M instead of 512K. link.dts is also being modified as appropriate. BUG=chrome-os-partner:6707 TEST=none Change-Id: I2cb6ef9319d57233f5254063d7c35f135fd34a52 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/12605 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-08Prepare a new flash map for Ivy BridgeVadim Bendebury
This is a copy of the Sandy Bridge flash map and the device tree with no modifications. Ivy Bridge requires more room for the MRC, and as such it requires its own flash map, the SB map and the dts wrapper will be used as the prototypes. BUG=chrome-os-partner:6707 TEST=none Change-Id: I25b5f7006f98991724da7b28ab6170a333495400 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/12604 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2011-12-07tegra: Disable setting up of GMI_CS6_N on T30/33Simon Glass
Changing the pinmux on this pin breaks T33, so remove it from the list. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: Iec78d9a3d1dcb5f0e45a5788f38a98d35048a378 Reviewed-on: https://gerrit.chromium.org/gerrit/12248 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-05tegra: Enhance board_panic_no_console() to support T30Simon Glass
On T30 PLLP may run at a higher speed, so support printing a panic message in that case also. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I741dd8da0317c56614fcca3e5e73830b3d4fe0d5 Reviewed-on: https://gerrit.chromium.org/gerrit/12246 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-05tegra: Add a clock rate parameter to clock_early_init()Simon Glass
Since PLLP can be set to two different values, make it a parameter to the function that sets up the PLLs. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d Reviewed-on: https://gerrit.chromium.org/gerrit/12245 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-01tegra: Move tegra_get_chip_type() to ap20.cSimon Glass
This function is better off in architecture code than board code. This is quite an invasive change unfortunately. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1 Reviewed-on: https://gerrit.chromium.org/gerrit/12244 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-01tegra: Add PLLP clock setting to fdtSimon Glass
This adds a setting for the required PLLP clock frequency. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I02ab35fcd496d4ac4cfa6b732fdd9a9b7eb2cc88 Reviewed-on: https://gerrit.chromium.org/gerrit/12242 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-22Remove second-stage U-Boot from 2MB firmware imageSimon Glass
There is barely enough space for U-Boot in the 2MB SPI flash. We are moving to eMMC firmware anyway, so for now let's remove the second-stage U-Boot from the image. This only affects Seaboard, not Kaen. BUG=chromium-os:19724 TEST=emerge chromeos-bootimage on Seaboard Change-Id: I6e3cadc2521b473cbea4ebbfeea2606780392fdb Reviewed-on: https://gerrit.chromium.org/gerrit/11942 Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-11-22UPSTREAM: Reduce build timesWolfgang Denk
U-Boot Makefiles contain a number of tests for compiler features etc. which so far are executed again and again. On some architectures (especially ARM) this results in a large number of calls to gcc. This patch makes sure to run such tests only once, thus largely reducing the number of "execve" system calls. Example: number of "execve" system calls for building the "P2020DS" (Power Architecture) and "qong" (ARM) boards, measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ================================== P2020DS 20555 15205 -26% qong 31692 14490 -54% As a result, built times are significantly reduced, typically by 30...50%. Change-Id: I6e8c7c37cd13c56cb64d0a410514f2b9dc2d5adb Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Albert Aribaud <albert.aribaud@free.fr> cc: Graeme Russ <graeme.russ@gmail.com> cc: Mike Frysinger <vapier@gentoo.org> (cherry picked from commit 77d94d2d86c055f015734cc4cd972a5de30fc5a2) Reviewed-on: https://gerrit.chromium.org/gerrit/11806 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-11-17BACKPORT: net: tftpput: Rename TFTP to TFTPGETSimon Glass
This is a better name for this protocol. Also remove the typedef to keep checkpatch happy, and move zeroing of NetBootFileXferSize a little earlier since TFTPPUT will need to change this. (cherry-picked from e4bf0c5) Change-Id: I90d03045de0231553a693f7119bdcc67a908e3c9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11796
2011-11-16arm: Tegra3: fdt: add display (LCD/PWFM) values for Tegra3Tom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=Built Waluigi AOK, ran OK to cmd prompt Change-Id: I18ad5386958f456bf9bc819de5affc4cb5bae267 Reviewed-on: https://gerrit.chromium.org/gerrit/11716 Reviewed-by: Tom Warren <twarren@nvidia.com> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-15arm: Tegra3: clear IO_RESET bit in pinmux registersTom Warren
Based on Tegra3 TRM, once E_18V bits in PMC are programmed, all IO_RESETs need to be cleared on LV blocks. If not, GPIO settings on related LV pins will always be set to low even if it is set to high. Specifically, it is observed that when IO_RESET bit is not cleared in VI_D4 pinmux register, the output of GPIO on VI_D4 (PL.02) is always low. That causes LVDS shutdown all the time. Also needed for SDMMC4 pins when booting from SPI. BUG=none TEST=built and booted on Waluigi, read/write SD/MMC data OK Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: Iaf84dc39375a49ceb3284dd1d48a8af3a0145175 Reviewed-on: https://gerrit.chromium.org/gerrit/11495 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-13spi: rename tegra2_spi to tegra_spi in prep for tegra3Che-Liang Chiou
BUG=chromium-os:21033 TEST=build seaboard successfully Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811 Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11471 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-04Introduce ability to use hardware SPI mapping for read accesses.Vadim Bendebury
On X86 systems the hardware maps the bootprom SPI flash chip into the top of memory address range. This could be used for accessing all information in the SPI flash. The vboot-reference code requires access to FMAP sections containing cryptographic information, and as of today, u-boot reads the whole sections, which are 64 KB in size, even though the actual areas accessed by vboot-reference are much smaller. A much faster way of accessing this information would be just passing around pointers to the appropriate memory areas. This would eliminate one copy, and also would make sure that only the areas actually accessed get fetched from SPI flash. This patch provides this ability trying to keep code changes to a minimum. New feature is enabled by defining CONFIG_HARDWARE_MAPPED_SPI. The firmware storage API for file reads changes when the new configuration option is set: a pointer to pointer to buffer is passed to the read_spi() function instead of a pointer to buffer. When the new feature is enabled the read_spi() function sets the pointer value to point to the requested data instead of copying the data into the buffer. A new data type is introduced (read_buf_type), which is set to be a (void *) if the new feature is not enabled, or (void **) otherwise. This type is used as the buffer pointer in the spi_read() function. Code allocating/freeing buffers used to keep data read from SPI flash is now conditionally compiled. Call sites for the spi_read() function are modified to adjust the buffer pointer parameter (pass the address of the parameter instead of the parameter, when the new feature is enabled). gbb field access functions can be aliased to gbb_init(), as they all in fact do the same - read a certain section of the gbb area. This change does not benefit the ARM implementations, and makes the code more complicated that it should be. Some u-boot rearchitecture along with vboot_reference API enhancements could address this. A tracking issue (http://code.google.com/p/chromium-os/issues/detail?id=22528) has been opened for that. BUG=chrome-os-partner:6585, chromium-os:22528 TEST=manual . build a new stumpy firmware image . boot the stumpy, observe it start up chromeos. . assess the boot timing using the cbmem.py utility (this modification shaves in excess of 100ms off the boot time). . disable the new feature, build a stumpy image, observe that is still boots chromeOs. . run emerge-terga2_kaen chromeos-u-boot to confirem that ARM version builds cleanly. Change-Id: I4e6ab530d24f5771b5a86a48d3f3135101b469a6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11152
2011-11-03tegra3: Add pinmux settings (do not submit)Jimmy Zhang
This adds pinmux config settings for a generic T30 board. This is just an example - real code should do pinmux setting in the driver which is the only thing that can know what the settings should be. BUG=chromium-os:21033 TEST=build and boot on Seaboard, Waluigi Change-Id: Ia56fcfc55e6cce8ac8b75c31d0618182aaa16bf6 Reviewed-on: https://gerrit.chromium.org/gerrit/8705 Commit-Ready: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
2011-11-03Clean up MTRR 7 right before jumping to the kernelStefan Reinauer
This cleans up the rom caching optimization implemented in coreboot (and needed throughout u-boot runtime. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:6585 TEST=boot coreboot on stumpy Change-Id: I7242c9c2b0546c633be8fb8ebc815ed6e6fda4d1 Reviewed-on: https://gerrit.chromium.org/gerrit/11138 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-28mmc: tegra3: Add MMC support for Tegra3 (specifically, waluigi)Doug Anderson
BUG=chromium-os:21540 TEST=Able to talk to MMC1 on Waluigi w/ future config changes. Specifically: 1. mmcinfo 0 - works (shows info) 2. mmcinfo 1 - works (shows info) 3. mmc rescan 1; mmc part 1 - works (shows partitions) Change-Id: I730d3b91088f20ccf7ca20f3f31f7d59514af243 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/10661 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-28mmc: tegra: Rename tegra2_mmc to tegra_mmc in prep for tegra3Doug Anderson
BUG=chromium-os:21540 TEST=Built u-boot and booted u-boot on tegra2_kaen Change-Id: Id6f11512ea1a95bd57b600601b488ae20b34db2d Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/10808 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-25Turn on the skip-i8042 option on stumpyGabe Black
BUG=chrome-os-partner:6585 TEST=Built and booted on Stumpy. Change-Id: I81d01ee325527156bb045a310b9b489cc935456c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10626 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-25Implement board_i8042_skip for coreboot boardsGabe Black
This implementation, which overrides the default for chromeos/coreboot boards, skips initializing the i8042 controller if the skip-i8042 config parameter is non-zero in the flattened device tree. BUG=chrome-os-partner:6585 TEST=Built and booted on Stumpy. Built and booted on Alex and verified that keyboard input still works. Change-Id: I6d4c64fe3d1c007f4f3d8f0556c8c5a0528e0928 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10625 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-25pmu: Make pmu_read() and pmu_write() set the bus numberDoug Anderson
This means that callers of pmu_read() and pmu_write() don't need to manually set the bus number. This also removes the side effect where pmu_set_nominal() could end up changing the current i2c bus number. BUG=chromium-os:21540 TEST=Compiled; sanity check on Seaboard. Change-Id: I1e4abdb5b2f06e9e3bada3e709280f6092d15005 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10461
2011-10-25pmu: Make pmu_read() and pmu_write() usable without clock scalingDoug Anderson
BUG=chromium-os:21540 TEST=Compiled Change-Id: I9ea3fa2ae185417cc81881f69c4a5d1ae639917a Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10458
2011-10-25pmu: Allow inclusion of PMU code without turning on clock scalingDoug Anderson
We may want to use the PMU to adjust various voltages even if we don't have clock scaling. Separate these two conecpts. BUG=chromium-os:21540 TEST=Compiled for Seaboard Change-Id: I376afe7e795fd2dd8035186c58f48a552391b4d1 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10457
2011-10-25pmu: Move pmu.c exported function defs to non-arch pmu.hDoug Anderson
Previously the exported function definitions for pmu.c were split among board.h, emc.c, and the architecture specific pmu.h. Create a non-architecture-specific pmu.h and put them there. NOTE: The arch/pmu.h file should probably be removed eventually in favor of the device tree, since it really just defines how a particular PMU is used by a particular family of board. BUG=chromium-os:21540 TEST=Compiled for seaboard Change-Id: Ia026e3ff3f1f465be629cc8a348879d2d1564686 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10456 Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-10-25pmu: Move definition of abs() and stp() out of pmu header fileDoug Anderson
These two functions were only used in pmu.c, so there was no reason for them to be in the header file. They probably should be moved elsewhere eventually, but this is a better location than they were. BUG=None TEST=Compiled Change-Id: Ia13cfd0fd828589862bfd555c3a34d3b6b4bda1c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10455 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-10-20CHROMIUM: tegra3: i2c: Add i2c support for all but i2c4Doug Anderson
BUG=chromium-os:21540 TEST=With future config change, saw that I could run i2c probe on busses 0-3 Change-Id: Ibfad91a3e7360434111c7aa6d2ea45f73e9690fc Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10366 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-20tegra: Check for I2C support when using clock scalingSimon Glass
It is not possible to enable CONFIG_TEGRA_CLOCK_SCALING without I2C and the current error message is not friendly. Add an explicit message to the board file. BUG=chromium-os:19004 TEST=build for Seaboard with and without I2C and see that it gives an error in the second case but not the first Change-Id: I65b7f379c48ee5f737ea5a473954cfc69f457021 Reviewed-on: http://gerrit.chromium.org/gerrit/10248 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-20tegra3: Add T30 supportSimon Glass
This adds support for T30 init to ap20.c, and modifies the board file to cope with it also. The only thing missing at this point is the pinmux setup. BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: I3e75245c1fdb99bc15eadcf60b173e6f0d9bb56c Reviewed-on: http://gerrit.chromium.org/gerrit/8704 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-19CHROMIUM: tegra3: i2c: Move DVC semantics choice to device treeDoug Anderson
On the tegra30, it appears that the "DVC" i2c controller has been normalized and no longer requires special semantics for accessing it (it has also just been renamed to "i2c5"). This change makes it so that we don't pick DVC semantics based on the periperal ID, but instead allow the device tree to specify. BUG=chromium-os:21540 TEST=Compiled / booted on Kaen Change-Id: Idfd96d1193b5ac267c61416544c63cc03dab396d Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10279 Reviewed-by: Simon Glass <sjg@chromium.org>
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