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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit cba518b4bbe4b9dfccb21ffe3cd0929c1a420719)
(cherry picked from commit 5721e405c34985f5faa1e6ff4e0d3ca32dffa6e5)
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Note that this requires the SCFW in a version which provides access
to the PMIC I2C. Something which the regular SCFW should not do.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 582a98a218dab6ac5a13ebd1cbd7a16e4b8305f3)
(cherry picked from commit 906059a7abf413bc165101812fb916743dd8eee7)
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 6557f1c6c8f5c5e6a5585459ab77e3d994ffff81)
(cherry picked from commit 6efbcb8cd6740e60fc53f9033d60cc27f62b3c74)
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 969f430f983d602afd83b6dd75b299e51463eae9)
(cherry picked from commit 2963361493e0f3df76f3a25202a56a76e69fd63f)
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Initial board support for Colibri iMX8QXP using a copy of Apalis iMX8.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 62f0f03e1acb4bb6b0fcca8d4e9bd4d2df04ad33)
(cherry picked from commit be14c3ea1850e2614883c86b62fd1c3a1828eac2)
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 200ed432e13e93c4c094031fe4d4481998227139)
(cherry picked from commit ba4474ab3cf4ff30ebcfa58b15b5f95746346d07)
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Add support for interactive recovery of Apalis iMX8 QuadMax
config block.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 70cf26d9f5edcb6de6b2b70f1bf6a821e46be3dd)
(cherry picked from commit afc3024a826e61dc0ecc5d55b8dea96544ca9487)
(cherry picked from commit b15393500e633a40319c5f8cf3ad02010f4acddd)
(cherry picked from commit 5ada977a2dd9240d2dd071468d310af79379abfd)
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Add an optional -y parameter to 'cfgblock create’ to simplify
automation.
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit d909b68d7f9da189a16e3ead0a6454b715201e23)
(cherry picked from commit ace5cf96413d3c736148dcecd1481e4249b7c5f1)
(cherry picked from commit 31091506e79e4924f47bc20b1830d6beef9bd1d7)
(cherry picked from commit 674ffe96fb6d9264f2e9019c8d26fce5fb3588e3)
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If the module is in serial downloader mode, we do no longer read the
environment from eMMC. Therefor, the eMMC is unitialized when trying
to read the config block. Use mmc_init to initialize the selected
MMC device before using it.
Note: In case the MMC has already been initialized, the mmc_init
detects that and returns immediately.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Conflicts:
board/toradex/common/configblock.c
(cherry picked from commit 0520b532d77d238be8015d3041a95188e47945cc)
(cherry picked from commit 3cb5f6450c39678a6361620bd45c423a503895cd)
(cherry picked from commit 79d3008acaebc0d33ba8fc21ffe46f058416d4a3)
Conflicts:
board/toradex/common/tdx-cfg-block.c
(cherry picked from commit cdcc3a8660fa4254d6d3ca6932a7cd599c0f1662)
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Add Toradex config block support for i.MX8QM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 18426b50681e6cd64ab5977f0ba84efd3f7c4495)
(cherry picked from commit c6d0e1042170d273a5b5434abe867213155d5582)
(cherry picked from commit ae31e946da33510a352795de09aa1c0ea9fc8280)
(cherry picked from commit 0798437c661ef3ca11f84fb45b4cce5b7ac145d9)
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Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit c97ae21d2e87f673e7f249f30df154b2bf5472fa)
(cherry picked from commit e82aab70ddcc0ea46e342980648fd23e69396b94)
(cherry picked from commit efc8eb53cc3184c88d4b76459cd585fcd594e118)
(cherry picked from commit f06fc58f6e30607475dab127cdaa525417022c36)
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 3f5807fa41c1744f6d4a9f0b702fb01a31fd73a7)
(cherry picked from commit 77471afdd9b663b775a2d2a1acc383767268e343)
(cherry picked from commit 2cb9fd05afebb14e594a27cb33c19919f39fd142)
(cherry picked from commit e351d2f491361f678d71f34c3857fb09775a12dd)
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Remove GPIOs used on the validation board but not required on
Apalis iMX8.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 9a8a826591c490c0a11c4baeef31c73f482c0438)
(cherry picked from commit adf5a30588c4352fc78c59b0d0c04fd43c6dad25)
(cherry picked from commit b0cabfcfd6d5abd3f1a9d429acf3f44d5c76bb1d)
(cherry picked from commit 75abf4f9e22ba2e1b1673e2d0e72c926ab6578f2)
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NXP LPUART1 is used as Apalis UART1, which is the main console
on our Linux BSP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 360629c1fd6187de19d0f50feb85c725995e49cc)
(cherry picked from commit 63030dac6afc51d17b04d23ce41af4788f03717e)
(cherry picked from commit 7bbe1708e0cebf3432c234ea74f8d6fb632a023b)
(cherry picked from commit d58fa8f3247edc18bdbf716fa9a45bcf5fce9cb8)
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Make sure that all pins connected to the Micrel KSZ9031 PHY
are muxed. Properly reset the PHY after all muxing has been
applied. This makes sure that strapping is not overwritten by
the SoC default mux (particularly it makes sure that CLK125_NDO
is not driven low during reset).
Make sure to not use CONFIG_DM_ETH as it seems to break ETH
support as is.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit f0a1ceb6f5e2ab3b3618190541b1e7a9fd4c1e4a)
(cherry picked from commit 8f6405070189a8744c2f6a9d9a6e041554fb9046)
(cherry picked from commit 6f24c637fd7725a27249d6a950f587134f30b97c)
(cherry picked from commit 1b3c97e1eb50a56066820596a6b1b83da465af7f)
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The Apalis iMX8 module does not have PCA9557 GPIO controllers
on the module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit c80b3bfbe693d5a8851129f4878d0cd3a7325d13)
(cherry picked from commit 898ae105703cd0019a542bc0a17649339c934fa6)
(cherry picked from commit 69d385444efa79d2909f772c4a4b404d1bd7274d)
(cherry picked from commit 0f5887d5b80f8535a7f422b73d7a0bf4a4e445af)
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Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit fa3d4f980a515b135778a74ce1b7476f61ef20d0)
(cherry picked from commit 2ee92bc1dd56b44343079a5474d0fc4e79f28f4a)
(cherry picked from commit 649afbe0aec4089112772a49a7e6f7d34c3741a7)
(cherry picked from commit 81591346d11ffdf9a2442ad976390ffe0e61abda)
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Initial board support for Apalis iMX8 using a copy of NXP
iMX8QM ARM2 LPDDR4 board.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 68e401998ba0654292b7914b85433d8453202ec8)
(cherry picked from commit 6b9234fa1f5889f0eeecc6147afffbc859933c99)
(cherry picked from commit 0b7feded806717b4292615373ed6c018324b8ef5)
Conflicts:
arch/arm/cpu/armv8/imx8/Kconfig, file moved
(cherry picked from commit 393dd8dd4061833fcc3cfd85886d49160b515ce0)
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iMX8DX MEK board has similar design with 8QXP MEK. The major changes are
1. DDR changed to 16bits 1GB DDR part
2. USB3.0 is removed and only support OTG on typec port. (No SW change needed)
This patch adds new defconfigs and DTS file for this new board.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 5efb4275f6cfefb5dd342f2e498834b40b989883)
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The QoS setting is originally added in MLK-22001, but override when
update the DDR script for DLL-ON only support, so add it back again.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Update the ddr4 timing file for 2400mts & 1066mts for
dll-on mode only.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit f7ed1fd1416f15764cca13993a054963996f6c50)
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The SPL codes for both EVK and validation board set the MMC bus width
to 1 bit for both emmc and SD ports. This causes slow image loading.
Change to 8 bits for emmc and 4 bits for SD.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0859140a862ad1cc16f4e49247868595a6e62b38)
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Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.
The module also adds some commands:
- snvs_cfg: Configure the SNVS HP and LP registers
- snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
- tamper_pin_cfg: Change the configuration of the tamper pins
- snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit 75aa7f2254f0883aa14568ac32702b1ca15367e4)
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On i.MX8MN, we can only support DLL-ON mode only, so update the timing
to support 2400mts & 1066mts setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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The '0x20060' register is used for phy memory reset, should not be put
in the ddrphy config section, so remove it from the timing script,
otherwise, ddr retention can NOT work. Additionally, the'0xd0000'
register config in phy section is redundant, remove it too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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According to datasheet, the VDD_SOC should be 0.85v in suspend mode.
But current voltage is default 0.80v because we don't configure BD71837
BUCK1_VOLT_SUSP register.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.
Signed-off-by: Ye Li <ye.li@nxp.com>
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To align with other iMX8M platforms, use CONFIG_TARGET_IMX8MN_DDR4_EVK for
DDR4 EVK board and will use CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK.
Signed-off-by: Ye Li <ye.li@nxp.com>
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There is an divider on imx8mn will always divide 2 to flexspi root clock.
So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz.
After changing the root clock setting to configure SCLK to 100Mhz, found
the read data is not correct. Must enable the internal DQS pad loopback
to fix the problem.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Align using emmc loader when there is no Trusty OS for Android standard
boot in SD/EMMC.
Add hook for getting correct offset when load uboot.
Change-Id: I5898cf196e734ffaca1a513918a049ce504b14e9
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
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Should use IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK not the
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT for clrsetbits_le32. This cause
to clean other bits.
Because the GPR1 is 0 by default, so this typo does not cause any issue
but should be fixed.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add configs to support evk_imx8mm 4GB DDR board. The 4GB DDR will
be split into two banks, one is 3GB (0x4000_0000~0xffff_0000) and
another is 1GB(0x1_0000_0000~0x1_4000_0000).
Test: build and boot with or without trusty.
Change-Id: I02f6465fc5709b15fd76820edb846452d011dd56
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Since rng_init is used arch_cpu_init, we have to clean up BSS section
before it.
Also remove the unnecessary memset to global data, because
board_init_f_init_reserve already memset it. If we memset it in board_init_f,
the gd->malloc_base is reset to 0 and will cause early malloc problem
when CONFIG_MALLOC_F_ADDR is not set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add imx8mn_ddr4_evk_nom_defconfig to generate SPL and u-boot to force SOC
to nominal mode. So the VDD_SOC will be 0.85V and ARM will be fixed to 0.85V
with DVFS disabled in kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
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Add support for AIY 2GB DDR size. Wrap support for
3GB DDR board with CONFIG_AIY_LPDDR4_3G because of
the limited ocram size.
Test: build and boot on 2GB AIY board.
Change-Id: I04da60cc0d0b22c6c32ff705bcab4095068ba6ea
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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DDR efficiency improved to 78% while runing LCDIF,GPU,CPU
Signed-off-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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Update the ddr performance setting on i.MX8MN DDR4 EVK board.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add configs to support evk_imx8mn android build.
Test: build and boot on eMMC and sd.
Change-Id: Id5c63b31e45357d791425976358635c18de928eb
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add board level codes, header file, and defconfig for iMX8M Nano EVK
board. The board has similar design as iMX8MM EVK.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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change the ddr init to use the common driver init driver as
we used on EVK board.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Set the display resolution to 720p for 1G ddr AIY board to
save some memory.
Test: build and boot on AIY.
Change-Id: I3ed56b371f849ce217f2ca58529b4d3b39e285c5
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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initialize potential uninitialized variable with the type of"char*" to
be NULL in AVB. That "hashtree_error_mode" in code is manually specified
with a known value, the cases listed cover all potential value of
"hashtree_error_mode"
explicitly do a type cast for memcpy parameters.
Change-Id: Ie5d234422a273d6dab75585bd0d8eb81583707ca
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
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Reserve 32M memory for GPU on AIY 1G DDR board.
Change-Id: I566a4a027982c8d4e41f280162f2f3cd67f1f5cd
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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* The default configuration (via resistor stuffing) is DFP (host). This
means that on Type-C hosts fastboot won't work.
* Set to UFP to ensure fastboot works properly.
Change-Id: I2b63d95e08df70da43dee1f8f7bb59d1863943f4
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* There is an enumeration problem when using superspeed.
* This doesn't fix it with all hubs, but can enable fastboot to work on
some 3.0 hosts.
Change-Id: If4a603126b945bd8f84c3d6e975e1185530eb193
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* Bucks 1-4 will be reconfigured via DVS in the kernel.
* Buck 5 is explicitly set to 1.0V
* Regulator lock/unlock is added, this ensures that in warm or cold
reset the values will be set.
Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77
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Add support for DVT AIY 1G board, distinguish the board type
with the board id.
TYPE: ID:
Micron 1G 0x5
HYNIX 1G 0x3
Micron 3G 0x1
Test: Boot on AIY 1G/3G ddr board.
Change-Id: I3c7b6ebe8bc5d4e59917fcc3947e9ebfefc940da
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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previous setting can NOT meet the USB stream mode performance settting.
So use the default QoS setting on the i.MX8MM DDR4.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Update the lpddr4 timing config to align with the ddr tool
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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When flexspi is assigned to M4 for XIP, its power up/down will fail.
This is expected so don't need to give warning.
Signed-off-by: Ye Li <ye.li@nxp.com>
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