Age | Commit message (Collapse) | Author |
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We enable the pull-up resistor for i2c pad by setting the PAD_CTL_PUE.
But this requires to enable pull resistors first by setting PAD_CTL_PE on iMX8MM,
otherwise the pull-up won't work.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Allow iMX8QM mek SPL to boot from QSPI.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add spl implementation for iMX8QM MEK board.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add implementation for ARM2 LPDDR4 board
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Since we set the fdt_file value when running on iMX6ULZ. This
cause the saved fdt_file change be overwritten. So users can't
set to their own fdt_file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Since the mx6ulz don't have FEC, it needs to use USB2NET dongle
to connect network. We decouple the CONFIG_FEC_MXC with CONFIG_CMD_NET.
For 6ull, all defconfigs need to enable the CONFIG_FEC_MXC explicitly.
Another change is adding ${usb_net_cmd} environment for usb start command
in netboot scripts on 6ulz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Allow iMX8QXP SPL to boot from QSPI.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add SPL and u-boot support to load images from RAWNAND device when booting
from RAWNAND. The NAND SPL loads the FIT image from nandfit mtdpart at 64MB
offset of NAND. Users need uuu to burn the FIT image, kernel, DTB and rootfs
to all fixed mtdparts.
Since NAND SPL needs large BSS and MALLOC size, this patch also moves the MALLOC
pool to DDR, and enable MALLOC_F pool on OCRAM for all malloc before DDR initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add i.MX6ULZ support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Separate tcpc related operations with config CONFIG_USB_TCPC
so we can enable/disable this feature separately.
Test: Boot ok on both imx8qm/8qxp_mek.
Change-Id: I46ef775e8deb4443944c0e969a4ced67c11ac48c
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Add DDR4 init codes, u-boot dtb and defconfig to support DDR4 EVK.
The DDR4 EVK removed eMMC and Flexspi, but use NAND instead. Current
codes support to boot from SD and enable NAND access in regular u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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To support the uuu, pack the common qspi header with u-boot binary for
i.MX6/7 qspi u-boot.
Signed-off-by: Han Xu <han.xu@nxp.com>
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enhance memory controller performance and QoS setting
Signed-off-by: Tom.zheng <haidong.zheng@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit ae7b37d3ed72bad542c8e77db4bbc0325180d6d2)
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This commit is basically cherry-picked from:
commit ced8dc6ce85f2227a29a52d55836b73223e71e73
Author: Ye Li <ye.li@nxp.com>
Date: Mon Aug 20 23:35:20 2018 -0700
MLK-19263-2 imx8mq_evk: Adjust SPL malloc pool and stack address
Currently the SRAM is allocated to malloc pool due to large malloc
needed by USB SDP. The stack is moved to OCRAM. This causes a
problem when enabling HAB. The HAB authentication needs large
memory on stack, so after ATF image loaded, the stack overwrites
the ATF image in OCRAM and causes authentication failed.
This patch moves the malloc pool to DDR and set back stack to
SRAM. So SDP still can run with enough memory on DDR. And the
stack overwrite issue can be fixed by enough memory 24KB left on
SRAM.
This change also need to use a early malloc pool by defining the
CONFIG_MALLOC_F_ADDR. And in SPL codes, we have to adjust DDR init
before board_init_r.
Signed-off-by: Ye Li <ye.li@nxp.com>
Change-Id: I37e0d196296b6b25662dda3dbbbc265bdf6d983f
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Sync configs with BSP team to enable uuu for imx8m AIY board,
create new file imx8mq_phanbell_androidthings_uuu_defconfig
for uuu image build.
Test: uuu works on imx8m AIY board.
Change-Id: Ied7cbb6d45d084837495cec5eeb5b4947a0630c4
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Currently the SRAM is allocated to malloc pool due to large malloc needed
by USB SDP. The stack is moved to OCRAM. This causes a problem when enabling
HAB. The HAB authentication needs large memory on stack, so after ATF image loaded,
the stack overwrites the ATF image in OCRAM and causes authentication failed.
This patch moves the malloc pool to DDR and set back stack to SRAM. So SDP still
can run with enough memory on DDR. And the stack overwrite issue can be fixed by
enough memory 24KB left on SRAM.
This change also need to use a early malloc pool by defining the CONFIG_MALLOC_F_ADDR.
And in SPL codes, we have to adjust DDR init before board_init_r.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
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The hdmi rx firmware is appended to the end of u-boot binary,
load it in u-boot, this will increase the size of u-boot binary
by 128k.
Test: hdmi rx firmware loaded successfully on imx8qm_mek.
Change-Id: Ib8e8ecd70a35b56ba4498c21d8c4716f6ad6405a
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Change VDD_DRAM to 0.9V
Change-Id: Ia2d0672b2f31f18add6626ac2e23e66b8c421a75
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5139
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Change the VDD_3V3 and VDD_1V8 to lower one to save power.
Change-Id: I61f1f4ed8c6e036173d9adc5358db01bd9c835a2
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5144
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Decrease the phanbell DDR(1G + 3G) frequency to 1600
MTS, this may save some power.
Test: Boot ok on both 1G and 3G DDR board, the dram_core_clk
decrease from 800000000 to 400000000.
Change-Id: I73b78865e7691001a868061826f0211cb9927cee
Signed-off-by: Luo Ji <ji.luo@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5100
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Add 1G DDR support, distinguish different boards by the
Board ID, They are:
SAI5_MCLK: Board_id[6]
SAI5_RXFS: Board_id[5]
SAI5_RXC: Board_id[4]
SAI5_RXD3: Board_id[3]
SAI5_RXD2: Board_id[2]
SAI5_RXD1: Board_id[1]
SAI5_RXD0: Board_id[0]
Current Board ID for imx8m boards are:
AIY Micron 1G: 0x5c
AIY Hynix 1G: 0x56
AIY Mirconb 3G: 0x40
Wibo 3G: 0x00
imx8m_ref 3G: 0x00
Test: Boot ok on all imx8m boards.
Change-Id: I3d65931483f369c545632b660f04fc9da120547d
Signed-off-by: Luo Ji <ji.luo@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5093
Reviewed-by: guoyin.chen <guoyin.chen@nxp.com>
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Fix build warnings in u-boot.
Change-Id: I1944657d2d89a03c0d2303a22a09538dfaa5fd2c
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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i2c_setup calls force_idle_bus which calls
get_timer if SDA and SCL are not high. On the Pico
baseboard there are level shifters that pull SDA
and SCL high, but the test harness does not have
pull-ups on these lines. Because
board_early_init_f is called before timer_init the
call to get_timer was causing a divide-by-zero
error due to CNTFRQ not being initialized. Moving
the i2c_setup calls to board_init fixes this
issue. power_init_board (which uses I2C to
configure the PMIC) is called after board_init, so
this should be safe.
Bug:
Test: PMIC registers are read correctly on both
boards (DEV_ID=0x30 REV_ID=0x11)
Test: iMX7D SOM boots on Pico baseboard
Test: iMX7D SOM boots on test harness
Change-Id: Iecdd28f3177fe915a3b614565d8dfa6e20e6a842
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Since the u-boot gadget class drivers don't support super speed, if
we set DWC3 gadget driver to super speed, the device mode will meet problem
when using USB3.0 cable. So force the DWC3 gadget driver to high speed
for both SPL and regular u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable TZASC on i.MX 8mm.
There is a need on 8MM to enable
the BYPASS ID SWAP bit (GPR10 bit 1) in order
for GPU not to generated AXI bus errors.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Get such build error below due to the changes in tcpc.h
(MLK-19181-2: i.MX850: SPL enable usb support).
Fix the issue by removing unused tcpc and usb header files from spl.c
spl/board/freescale/imx8qxp_mek/spl.o: In function `tcpc_setup_ufp_mode':
spl.c:(.text.tcpc_setup_ufp_mode+0x0): multiple definition of `tcpc_setup_ufp_mode'
spl/board/freescale/imx8qxp_mek/imx8qxp_mek.o:imx8qxp_mek.c:(.text.tcpc_setup_ufp_mode+0x0): first defined here
spl/board/freescale/imx8qxp_mek/spl.o: In function `tcpc_setup_dfp_mode':
spl.c:(.text.tcpc_setup_dfp_mode+0x0): multiple definition of `tcpc_setup_dfp_mode'
spl/board/freescale/imx8qxp_mek/imx8qxp_mek.o:/home/leyoen/Workspace/u-boot-upgrading/u-boot/board/freescale/imx8qxp_mek/imx8qxp_mek.c:547: first defined here
scripts/Makefile.build:359: recipe for target 'spl/board/freescale/imx8qxp_mek/built-in.o' failed
Signed-off-by: Ye Li <ye.li@nxp.com>
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Pull down the DSI_EN gpio to disable mipi dsi panel before booting kernel.
This avoids display full yellow screen before kernel mipi driver probes
the device.
For MIPI2HDMI card, this DSI_EN gpio is not used. So nothing impact to it.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e73adc9a139f2e8bb92bda1631fa2f2391a8a5e3)
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As there is problem with super speed with SDP, we force the dwc3
usb speed to be high speed.
Signed-off-by: Li Jun <jun.li@nxp.com>
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Enable DWC3 USB support at i.MX850D platform
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Add new dts, config and defconfig file for DX DDR3 ARM2 board. Since
it does not have USB3.0 and SD, disable them in DTS and header file. Also move
gpio expander to i2c1 according with its schematic.
In defconfig, fastboot is default enabled due to we need uuu to program
eMMC.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e5b822615a5aa2fadb481002c286f35d996999f8)
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Add spl implementation for LPDDR4 and DDR4 iMX8QM boards.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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This adds the spl specific code for imx8qxp.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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dispmix & mipi phy power domain must be enabled before doing any
config for lcfif and dsi.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 240475ecb29aff22fb362ea39f3bf8e7045281db)
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Refact the lpddr4 init flow on i.MX8MM EVK board. board level only need
to provide the necessary dram init related parameter.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 72a06ef47c7c93de49730261adb8f251612d1883)
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Add the secure boot relevant environment variables to ARM2 and MEK.
When CONFIG_AHAB_BOOT is enabled, we will switch to boot flow:
1. Load the signed OS container to address 0x88000000
2. Using auth_cntr to authenticate the OS container. It will load the
kernel and FDT to destination addresses.
3. Using booti to boot kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit eb47b72c1c89deddeaa3b3618d8c28aca05cd4ad)
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Meet such warning during boot with EPDC splash screen enabled, because the
flushed waveform buffer size is not aligned to cacheline size
CACHE: Misaligned operation at range [ff027d00, ff270d99]
Since we have enough 4MB buffer allocated, round up the flushed size to
eliminate the warning.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 211af0d11f4472d7575b54ad5d14e79f77e71b6a)
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Add board level codes for enabling splash screen on imx8mm EVK. We
support two different display connecting to MIPI DSI miniSAS interfaces:
1. MIPI2HDMI daughter card (default)
2. RM67191 OLED panel
Users can set "panel" env vairable to "MIPI2HDMI" or "RM67191_OLED" to
switch them after reboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 41f896ce26aa0f518b5cacb1d9660a0a085ee691)
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Setup the mipi_dsi_northwest driver and register a the HX8363 panel
device to mipi dsi bridge in board codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fca13cf24f4a7be15747d92e4622d5e3749f80ef)
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with tzasc enabled, the GPU is generating AXI bus errors.
currently reverting the patch while debuging
This reverts commit ccec5df5aaf583c6d261d5c64a1d668d0e001ed8.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Change to use clock API "clock_set_target_val" to set DRAM APB clock
root for DDR4 init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fc72bf2b5ce59994765da6c5e66745d037e05237)
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Some debug codes in DDR init are used, which set NOC and NOC APB clocks to 25M
OSC and causes slow booting and poor performance in SPL and u-boot. Change to
original codes which only set DRAM APB clock to 200Mhz and use clock API to
implement it.
Some trailing spaces are also trimmed in this patch.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d2d2e56b29c136793bd4b398ce16b3e5442c7f72)
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Add SPL/u-boot board codes and DDR4 settings for iMX8MM DDR4 validation board.
DDR overnight stress test is passed.
Supported modules:
SD/eMMC, I2C, ENET, Flexspi, UART and USB.
Build config:
imx8mm_ddr4_val_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 6045484796a87a31938a19d2d8fa2ae095804586)
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Enable the SPL SDP for iMX8MM EVK. So that when booting from USB serial
download mode, the SPL will enter SDP to download FIT image from USB host
(uuu tool) and boot into FIT image.
The SDP driver needs larger malloc pool size, so extend the SPL malloc pool
to 12KB and reduce the SPL BSS MAX to 4KB because BSS actual size is about 1KB.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable TZASC functionality.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by : Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 225f888b0960f817fc96842e35f48c7e2d4213d3)
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We are targeting let uboot loading images from emmc to boot android.
Currently only emmc1 is enabled, so other devices are disabled.
Also change memory layout according to VM layout. The memory layout
needs to be samesize as what you configured in as "memory = "3584"".
Add a new dts dedicated for this kind uboot, add a new defconfig
to select CONFIG_XEN/CONFIG_XEN_DEBUG_SERIAL, deselect CONFIG_DM_SERIAL,
select CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK, and disable some devices
compared with imx8qm_mek_androidauto_defconfig.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a4e932cae433b9d2e1cff6a94b12e4abcac45543)
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Add the board_ehci_usb_phy_mode in board codes to overwrite the default
in ehci-mx6 driver. Since the DRP is enabled in tcpc, we use the feature
in board_ehci_usb_phy_mode to detect current role. Then driver can
assign correct role type to board_usb_init and board_usb_cleanup.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5a4408c72736be3927e7132e01b7886b93451bbc)
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Enable the DRP, so the tcpc can try to toggle the role. This helps to
determine the current role when we don't know whether device or host is
connected.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9617e630151731aa42cbad95c70e7f3526cf242e)
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Since the PD switch callback is added to tcpc driver, we move the
NX20P3483 settings to this callback to exit DB and set OVP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 7be626ee7d565712db0aac12cf31f5d867275267)
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Introduce a callback function to setup external PD switch. When PD
process is enabled, we call this function only when SINK_VBUS is enabled
to avoid system power shut down.
When PD process is disabled, since the tcpc and external PD switch may
still in dead battery mode, set them to exit dead battery.
This patch is used to fix two issues on iMX8MM EVK:
1. When power on the board, by default the PTN5110 and NX20P3483 will
enter dead battery mode. But for some cases, like timing issue for PTN5110
and NX20P3483 (refer rework instructions CQ6), and when dual port are plugin
power sources. There are possibility the PTN5110 does not enter dead battery mode,
but NX20P3483 is in dead battery. So for the USB2 primary power port, we has to check
SINK_VBUS before NX20P3483 exits dead battery, otherwise the system power will shut down
2. For the USB1 port, when dual port are plugin power sources. We need to set both
PTN5110 and NX20P3483 exit dead battery. Otherwise this port can't work for normal
host/device mode.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 30004c6b35a5f0b8460f534d324f9bde01325373)
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