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Add support for DDR4 board in u-boot.
Main changes are the SD card slot and ddr
type
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Add board codes, configurations, DTS and DDR initialization codes for the
DDR3L and DDR4 ARM2 boards.
Supported modules
- DDR3L ARM2: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
- DDR4 ARM2: Two RANK DDR4, SD, NAND, RGMII ENET, UART.
NAND read/write/erase is ok in u-boot, NAND SPL boot will be tested later
when tool is ready.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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Add 400Mhz, 600Mhz and 800Mhz frequencies for dram pll init function to
support DDR3L/DDR4/LPDDR4.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Due to RGMII interface timing requirement for imx8qm/qxp mek and arm2
board, it needs to enable RX clock delay.
It should not depend on HW default status since kernel may clear the
bit only on imx8qm/qxp platforms, then reboot test will cause uboot
networking failed.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add defconfig for tee support;
Enable the TZASC support;
Add env config for tee support.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add different defconfig for optee;
Enable the TZASC support;
Add env config for tee support.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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1. With this change, no flickering when LCDIF + MIPI-DSI
in 720p60 single display case
2. With this change, no flickering when DCSS in 4kp60
while running 4x memtester at the same time
side effect:
GPU resolve performance downgrade ~20%, no obvious impact
to non-resolve GPU cases.
Signed-off-by: Jian Li <jian.li@nxp.com>
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The EVK board does not use external pull up resistor for SD CD pin, it requires
the pad to be configured as pull up, otherwise the signal level is always low even
the card is not inserted.
This patch configures the pad of CD and RESET to pull up to align with kernel,
although there is already a external pull up for RESET.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add back LPDDR4 performance register settings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Support DDR3 ARM2 board.
Most parts are same as LPDDR4 ARM2 board, so share code
with LPDDR4 ARM2.
The DRAM size is 1GB on DDR3 ARM2 board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Change to use more generic name for DDR files and public functions used in SPL,
not specified to LPDDR4.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.
mx7d arm2 board not supported now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add different defconfigs
Enable Trustzone.
Update env to runtime boot OP-TEE.
To 6QP SDB, TZASC enabled, need board rework and new ddr script.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.
To 6QP AUTO, TZASC not enabled now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Implement wdog reset in SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Android needs to use USBOTG port on MEK base board for fastboot (USB device mode).
Add relevant node to DTS and update configurations to enable the port in android build.
Signed-off-by: Ye Li <ye.li@nxp.com>
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rom_pointer[0] contains the base, rom_pointer[1] contains the size.
When TEE enabled, if not reserve the space, uboot relocation may
overwrite TEE or trigger fault when TZASC enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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On our i.MX8MQ EVK board, we will support three frequency point:
1. 3200mts, DDRC core clock is 800MHz;
2. 400mts, DDRC core clock is 100MHz;
3. 100mts, DDRC core clock is 25MHz.
The 1D training flow need to be run once for each frequency. The
PHY training updated to support training different frequency point.
Additionally, the DDRC's registers of other frequency also need to
be configured.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Change the DDR calibration flow from 1D training to 2D training.
the hardware can use an this optional 2D training to optimize
the PHY and DRAM setting in both time and voltage.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Support SPL FIT. Uboot text base are also modified, because spl
will load fit to address before text base of uboot.
According to new ATF request, modified the SPL stack/bss to OCRAM_S
space.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Duplicate defconfig for pico-imx6ul
by picosom-imx6ul-trusty_defconfig.
Change-Id: I559124e8e94eb40f943e0c4d68b9a6da821c6f41
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
(cherry picked from commit f019c752e4ac1ab210b9a09a00d48a6eaf3fefb3)
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Change-Id: Iee122d36d83bc6e1ae007fb2f2053c6e9e7fc2a2
Signed-off-by: ji.luo <ji.luo@nxp.com>
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Change-Id: I0aa12c5092953804e724c0534f2e81abd9ee47d5
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
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Add build config, dts and board codes for i.MX8QM MEK board. Supported
peripherals: UART, eMMC/SD, ENET, I2C, USB TYPEC DFP mode, flexspi.
DTS is ported from kernel commit a4fff857ea5f0a6513b943e0b0b842d5008785f1,
and enable more peripherals.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Enable the USB3.0 XHCI driver to support host mode on MEK board.
The USB3.0 typec on MEK board uses PTN5110 TCPC as cc logic and power control. Different like
the device on ARM2 board, this IC needs driver to control and get status through I2C bus.
In this patch, we simply call the TCPC API to set to DFP mode, check the CC status for SS MUX select
and enable source VBUS power. When the USB host is shutdown, disable the VBUS power.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add an simple driver for USB typec port controller in freescale common codes.
The functions in this driver help to initialize the TCPC, set and work with
fixed DFP role.
Will improve it later to support UFP and move to driver directory.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Export the board_name and board_rev for these boards:
- 8MQ EVK
- 8QM ARM2
- 8QXP ARM2
- 8QXP MEK
These two variables are used by an autotest u-boot script,
to request the needed BSP files.
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Found kernel won't be loaded when UART does not connect to the board. This is
because UART received one data with frame error in this case, and stop in
u-boot console.
The root cause is we set wrong pad setting for UART. The pad should be set
to pull up not pull down. The pull down will cause problem to UART START bit.
This patch fix the UART pad to 0x600020 (input and output, high drive strength,
and pull up).
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The MEK board has two display ports, we enable the LVDS0 as default display. User
needs to connect miniSAS LVDS to HDMI card on the CPU board and set "panel" env variable
to "IT6263" to enable the display.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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According to the MX6DL datasheet (IMX6SDLCEC Rev. 5, 06/2015)
"LDO Output Set Point (VDD_ARM_CAP) = 1.125 V minimum for operation
up to 396 MHz."
So change the VDD ARM to 1.15V (with 25mv margin).
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
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Add USB0(type-c) config and PHY init to enable device mode.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
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When using DM xhci and ehci drivers, we can support both two controllers
(OTG and USB3) at same time. Refactor the QM and QXP ARM2 board codes and
configurations to enable them.
Because the xhci-imx8 driver will initialize the clock, and DM framework
will enable power domains, so only keep the power up in board level codes
for non-DM driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng@nxp.com>
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Added GPIOs to enable the Mini SAS display boards at startup.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
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Since the DM framework and ehci-mx6 driver will enable the power domains
for USB controller and PHY via power domain driver. No need to call
the power on function in board level.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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NAND module is pin conflict with SD/eMMC on i.MX8QXP ARM2 board,
add new config to disable SD/eMMC when booting from NAND.
Signed-off-by: Han Xu <han.xu@nxp.com>
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Enable DM_ETH for i.mx8mq evk board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enable pinctrl/dm mmc/dm i2c/dm regulator and pmic.
Since we do not enable DM for SPL, so move non dm
code to spl file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Allow be omited by DM
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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This patch enables the power domain driver for i.MX8QM and QXP boards in defconfig files.
The devices with using DM driver will be powered on automatically by DM framework. So
we remove the power relevant codes for them.
For devices with non-DM drivers, we updates the board/SoC codes to use power domain driver API.
So that we can use power domain driver to manage them.
The only exceptions are:
1. UART0 at board_early_f, this is very early stage, that power domain is not ready.
2. Power up secondary cores and M4 cores. These resources are not peripherals and
are not in power domain tree.
Additional, benefiting from power domain driver, We have implemented the function "power_off_pd_devices"
to power off all active devices. No need to explicitly power off them in board_quiesce_devices.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
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Support MFG.
1. When ROM jumps to SPL, SPL saves ROM context. After SPL successfully
initialize DRAM, SPL will restore ROM and context and back to ROM.
During this flow, SPL does not do any USB configuration to avoid
breaking the connect between ROM and Host PC, because we rely on
ROM to continue serial download with Host.
2. Add MFG env to support kernel boot correctly.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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This patch enables the pinctrl driver for i.MX8QXP ARM2 and MEK boards.
For DM enabled driver, the iomux pins can be set by pinctrl driver. So
the board codes don't need to set iomux explicitly for these DM enabled modules.
Also update the DTS file for i2c pins settings.
Signed-off-by: Ye Li <ye.li@nxp.com>
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This patch enables the pinctrl driver for i.MX8QM ARM2 board.
For DM enabled driver, the iomux pins can be set by pinctrl driver. So
the board codes don't need to set iomux explicitly for these DM enabled
modules.
Also update the DTS file for some module's pins settings.
Signed-off-by: Ye Li <ye.li@nxp.com>
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On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing.
And due to MMDC limitation, the script we get from IC team is only doing
CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might
cause CS0 can NOT be accessed any longer.
Because of this HW issue, we found the high 512MB memory needs more time to
be stable. Since the u-boot relocates itself to highest address after booting,
so this will cause issue.
To work around it, we just limit the u-boot running at low 512MB memory.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add imx8qxp mek android config
Below config is commented out due to USB not ready for this board
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_CMD_FASTBOOT
Change-Id: I024156d445ed880ddd7a8dc15d94c81bb0a71b5e
Signed-off-by: guoyin.chen <guoyin.chen@nxp.com>
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Fix SD3_VCC power rail enablement on DM MMC build
Add in pin control hog group MX6QDL_PAD_GPIO_18__SD3_VSELECT
pad for early power on of SD3_VCC power rail.
Add cd-gpio property.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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We assign the DDR memory from 0x88000000 to 0x8FFFFFFF to M4 on QM and QXP.
The M4 can allocate this memory by two ways, in SCD or u-boot.
There are 3 things needed to change in u-boot:
1. Move the u-boot INIT SP address to first 128M memory to avoid conflict with M4 memory.
2. The memory regions may be allocated in SCD or ATF. So we can't staticly set the memory
bank information in u-boot, need to get it from owned memory regions.
3. u-boot addes the memory reserve node to DTB to pass the info to kernel, no matter
the M4 memory is reserved in SCD or u-boot. So kernel won't access M4 reserved memory.
The codes for M4 resources and memory regions allocated by u-boot will be added
later when they are finalized.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Setup the BB_PWR_EN GPIO to high to enable the 1.8v power on base board.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the board file, head file, build config and DTS for i.MX8QXP MEK.
Enabled SD/eMMC, FlexSPI, UART, LPI2C, I2C MUX, IO EXP and Ethernet.
DTS is based on kernel patch (commit 86203e3c136836d6b01d5e00ac52c561014f1cab),
and add support for i2c mux, ioexp, second ethernet on base board and flexspi.
Signed-off-by: Ye Li <ye.li@nxp.com>
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