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2024-05-28toradex: tdx-cfg-block: add verdin i.mx8m mini 0090 pid4toradex_imx_lf_v2022.04Emanuele Ghidoli
Add new PID4 0090 Verdin iMX8M Mini Quad 4GB WB ET to support the new hardware variant. Upstream-Status: Submitted [https://lore.kernel.org/all/20240528095941.872693-1-ghidoliemanuele@gmail.com/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2024-05-28toradex: tdx-cfg-block: add verdin imx95 sku 0089 pid4Emanuele Ghidoli
Add new PID4 0089 Verdin iMX95 Hexa 16GB WB IT to config block handling. Upstream-Status: Submitted [https://lore.kernel.org/all/20240528095941.872693-1-ghidoliemanuele@gmail.com/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2024-05-28toradex: tdx-cfg-block: add aquila am69 sku 0088 pid4Emanuele Ghidoli
Add new PID4 0088 Aquila AM69 Octa 32GB WB IT to config block handling. Upstream-Status: Submitted [https://lore.kernel.org/all/20240528095941.872693-1-ghidoliemanuele@gmail.com/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2024-05-28board: toradex: verdin-imx8mm: increase maximum addressable ram to 4GBEmanuele Ghidoli
Add support for SKUs with higher memory sizes. Actual memory size is auto-detected. Upstream-Status: Submitted [https://lore.kernel.org/all/20240528095941.872693-1-ghidoliemanuele@gmail.com/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2024-05-28board: toradex: verdin-imx8mm: add 4 GB lpddr4 memory supportEmanuele Ghidoli
Add support for MT53E512M32D1ZW-046 IT:C memory. This 4 GB memory has 17 row bits instead of 16 and requires 380 ns of tRFC (tRFCab) instead of 280 ns due to increased channel density to 16 Gb. Both modifications are retro-compatible with previous memories. Upstream-Status: Submitted [https://lore.kernel.org/all/20240528095941.872693-1-ghidoliemanuele@gmail.com/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2024-03-08toradex: tdx-cfg-block: add 0087 i.mx8m mini product variantJoao Paulo Goncalves
Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20240308141801.49081-1-jpaulo.silvagoncalves@gmail.com/] Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
2024-02-19Merge tag 'lf-5.15.71-2.2.2' into toradex_imx_lf_v2022.04Max Krummenacher
This pulls in the following commits: git log --oneline --no-merges ^HEAD lf-5.15.71-2.2.2 14b6c8f3e3b MA-20886 imx8ulp: Boot from recovery mode when pressing key 62ad7799b6c LF-7602: Device tree fixup based on compatible string b35420da607 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash() 918dbf78bbb MA-20872 Revert "MA-18775 system will hang about 3s when boot up kernel" ed2c3cbd6ac MA-20814 add fastboot command to erase u-boot env a6762e28bf0 LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd d23cfa09767 LFU-426: qspihdr: Coverity Issue: unchecked return value 413b08f841f MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name e91a047f54f LF-7382: fastboot: improve emmc write speed 205680f9f4b LFU-428 imx8ulp: Add warning for CAAM non-secure state failure f405551dcc1 LF-7369-2 clk: imx93: update LPCG control API 676831be672 LF-7369-1 clk: imx: implement a clock gate driver for i.MX93 94c5bb2eb83 MA-20507-7 trusty: fix dereference null return value 6933487b4df LFU-427 imx93: Print ELE FW version 15b1ebb00cc LFU-393 imx93: Add reset cause print f3b75e3317d LF-7332 imx8/ahab: sha256: enable image verification using ARMv8 crypto extention 330e2634143 LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check 58ba744cbad MLK-26034 imx6: Disable LCDIF clock before jumping to kernel ae396d343a3 LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd 0a99627b60e LFU-422-2 imx8ulp_evk: Enable the GD25LX256E support c6c06de038f LFU-422-1 mtd: spi-nor: Add GigaDevice GD25LX256E NOR flash 032fab5e127 LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK d9f477625d3 LF-7332 armv8: SHA-256 using ARMv8 Crypto Extensions 53689e4f7db MA-20667 set metadata partition of type f2fs f824cd01955 LFU-415 net: fec_mxc: Skip recv packet process when fec is halted 4e7c44e1f33 LFU-419 arm: dts: imx8mp: fix flexspi nand reg 957bdd9c925 LFU-418 imx8ulp: upower_hal: make code cleaner 361b23b98ed Revert "MLK-25478-1 efi: add Platform-Reset-Attack variables" e1ed0611b5e Revert "MLK-25478-2 efi: clean memory and reset MemoryOverwriteRequestControl" 4998fef38a5 Revert "MLK-25478-3 workaround: disable verify time of signer and signee." 320096439b6 MA-20738 imx8ulp: bumps CONFIG_LMB_MAX_REGIONS c244bdfd76c LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature 026521c7d65 LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support a555a21be69 LFU-413 imx8ulp_evk: Remove CONFIG_BOOTDELAY=0 from ND defconfig aaead5a2b8d LFU-416 imx: cmd_dek: Fix build warning in blob_encap_dek 933a3b25fe3 LF-7234 enable CONFIG_CMD_CRC32 and CONFIG_CRC32_VERIFY 97fc905e7f7 LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting aa4ebb66199 LFU-414 imx8ulp: clock: Update clocks to meet max rate restrictions 63d0579f397 LFU-410 imx: ele_ahab: Add ahab_sec_fuse_prog command 266dddae454 LFU-412 configs: imx93_evk: shrink mem= for jailhouse 5703d3ae37e LFU-411 imx8ulp: Always enable MIPI_DSI power switch 32965eb52f7 LFU-392 imx8ulp: upower: replace magic number with macro beb5e5e3303 MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default bb45dd592db LFU-408 imx93evk: config the pmic standby voltage for buck1 25e38cb4762 LFU-407-02 ddr: imx9: Change the saved ddr data base to 0x2051c000 a8fef10ab92 LFU-407-01 configs: imx93: Update spl stack & bss base address 8731024fe7e LFU-406 mx6ul/mx6ulz: Fix build break caused by RNG patch a95afe08769 LF-7238 imx9: soc: Remove OPTEE memory from DRAM bank and MMU 19c3fdebf8d LFU-403-4 imx93_evk/qsb: Enable TMU sensor driver e1703ec06a4 LFU-403-3 iMX93: soc: print current CPU temperature 050a94e6365 LFU-403-2 DTS: imx93: Update TMU node to sync with kernel 91e711a565c LFU-403-1 thermal: imx_tmu: Update TMU driver to support iMX93 78749666dd3 LFU-402-3 imx93_evk/qsb: Use API to set max ARM clock 401b9824f92 LFU-402-2 iMX93: clock: Add API to set max ARM core clock e4722baa5af LFU-402-1 iMX93: soc: Get market segment and speed grading 432a4af9608 LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers 53f06207782 LFU-399 imx8ulp: Reconfigure MRC3 for SRAM0 access 48a2221acc9 LFU-395 imx93: Add fused parts support d8760a74793 LFU-398-7 imx93_9x9_qsb: Enable Flexspi NOR support 1f500a59670 LFU-398-6 imx93_qsb: Enable M.2 VPCIe_3V3 and deassert SD3_nRST ba4f72198f5 LFU-398-5 DTS: imx93-9x9-qsb: Add flexspi NOR nodes and pinctrl d9f563336f7 LFU-398-4 imx93_11x11_evk: Enable Flexspi NOR support c56f2132d53 LFU-398-3 imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST b6cbe6b1416 LFU-398-2 DTS: imx93-11x11-evk: Enable and update flexspi NOR c45c4fb791b LFU-398-1 DTS: imx93: Update flexspi node in DTSi fab973fe1df LFU-397 imx8m: clock: not configure reserved SRC register 4881ba99fa4 LFU-396-7 imx93_9x9_qsp_defconfig: support splash screen 60e0e629f99 LFU-396-6 arm: dts: add imx93 9x9 ontat panel dts fffc330cf1a LFU-396-5 imx9: clock: add 300MHz fracn pll table ef6a3d9cc38 LFU-396-4 video: nxp: imx: add Add i.MX93 parallel display format encoder driver 5f414738a5f LFU-396-3 video: nxp: imx_lcdifv3: support VSYNC/HSYNC active low 21eb66fe1f8 LFU-396-2 video: nxp: imx: dsi: force DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH 88132ed0b4e LFU-396-1 video: simple_panel: make backlight optional 65287dc074d LF-7055: video: imx: Add set_parent calls to LVDS initialization 167f65006fb MLK-26021 imx93: add 9x9 qsb lpddr4 board 0a6297a290e MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default 8789f3ca3e4 PLATSEC-1781-2 MX6: Device tree fix-up 60555c4a445 PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP 48b1d6e34fd MA-20149 set fs type of android partitions 9710cc4840e LFOPTEE-177 imx93evk: enable cmd_dek command f0721d67f03 LFOPTEE-177 imx8ulp: enable cmd_dek command bf07f5166bf LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support 6de56c3f629 LFOPTEE-177 s400_api: add DEK Blob generation Conflicts: drivers/crypto/fsl/fsl_hash.c commit 41b2182af73 ("crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()") Both NXP and TXD branch did cherry-picking that commit, but NXP additionally removed a debug print (not present in master) while the TDX branch did not. Resolved by doing it the NXP way. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2024-01-31toradex: tdx-cfg-block: add 0086 i.mx8m mini skuJoao Paulo Goncalves
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20240131173204.100407-1-jpaulo.silvagoncalves@gmail.com/] Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
2023-09-12board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ↵Andrejs Cainikovs
ERR050805 Update lpddr4 configuration and training using updated spreadsheet and tools from NXP using data from previous spreadsheet and verified toward datasheet: - MX8M_Mini_LPDDR4_RPA_v22.xlsx - mscale_ddr_tool_v3.31_setup.exe The most relevant update is related to errata ERR050805: "DRAM: Controller automatic derating logic may not work when the LPDDR4 memory temperature is above 85 °C at initialization" Other relevant fixes: - DRAMTMG7 register: corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4) - RANKCTL register: corrected calculations for ODTLon and ODTLoff to follow the JEDEC specification - ADDRMAP7 register: added support for 17-row devices As per errata ERR050805: An issue exists with the automatic derating logic of the DDR controller that only samples the LPDDR4 MR4 register when the Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the LPDDR4 memory is initialized and starts operation above 85 °C (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will not be set. The DDR Controller will therefore not automatically adjust the memory refresh rate or de-rate memory timings based on the LPDDR4 memory temperature. This may cause the controller incorrectly setting the refresh period, potentially cause the LPDDR4 memory losing data contents and lead to possible data integrity issues above 85 °C. Errata provides three possible workaround options, while option 2 is the most reasonable: Disable the automatic derating logic of the DDR controller and apply fixed x2 refresh rate (0.5x refresh). This option is suitable for designs that are expected to boot at or above 85 °C and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following conditions: 3b101: 0.25x refresh, no de-rating 3b110: 0.25x refresh, with de-rating 3b111: SDRAM High temperature operating limit exceeded [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf Upstream-Status: Pending Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-09-04ARM: imx8m: verdin-imx8mm: Drop bogus content from spl_board_init()Marek Vasut
The current implementation of spl_board_init() USB boot handling is not correct, the MX8MM BootROM v1 does not support SDP load when re-entered from U-Boot SPL, it is up to U-Boot to perform the next stage load using its own internal CI gadget driver and SDP protocol implementation. Drop the spl_board_init() to let SPL continue with normal load in case the SDP support is enabled. Upstream-Status: Backport[f687c1ef4fdf14faea16c13b1eaac5496dee39df] Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-18toradex: tdx-cfg-block: rework display adapter name handlingMax Krummenacher
Rework the rather big array of zero length strings with 4 entries of actual display adapter names to a array of structs which ties a pid4 to its correspondent human readable string. Provide an accessor to get the string for a given PID4. Upstream-Status: Submitted [https://lore.kernel.org/all/20230718090734.20357-4-andrejs.cainikovs@toradex.com/] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-07-18toradex: tdx-cfg-block: rework carrier board name handlingMax Krummenacher
Rework the rather big array of zero length strings with 4 entries of actual carrier board names to a array of structs which ties a pid4 to its correspondent human readable string. Provide an accessor to get the string for a given PID4. Rework the user of the information to use the accessor. Note that check_pid8_sanity() is used for early samples of Dahlia and the development board. Yavia isn't affected. Upstream-Status: Submitted [https://lore.kernel.org/all/20230718090734.20357-3-andrejs.cainikovs@toradex.com/] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-07-18toradex: tdx-cfg-block: add yavia carrier cfg block infoMax Krummenacher
Add the Yavia Carrier board name string to the known carrier board list. Upstream-Status: Submitted [https://lore.kernel.org/all/20230718090734.20357-2-andrejs.cainikovs@toradex.com/] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-15toradex: tdx-cfg-block: add 0070 verdin i.mx 8m plus quad skuEmanuele Ghidoli
Add new i.MX 8M Plus Quad SKU to ConfigBlock handling. 0070: Verdin iMX8M Plus Quad 8GB WB IT This SKU is identical to 0066 but supporting Industrial Temperature range. Upstream-Status: Submitted [https://lore.kernel.org/all/20230515130641.26028-1-francesco@dolcini.it/] Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-04-03board: colibri-imx8x: initialize snvsAndrejs Cainikovs
Initialize Secure Non-Volatile Storage, aka SNVS. Upstream-Status: Submitted [https://lore.kernel.org/all/20230403111426.61327-3-andrejs.cainikovs@toradex.com/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-04-03colibri-imx8x: print firmware versionsAndrejs Cainikovs
Print firmware versions during U-Boot start: BuildInfo: - SCFW f5623878, SECO-FW c9de51c0, IMX-MKIMAGE 0, ATF c6a19b1 - U-Boot 2022.04-00335-g65192567f81-dirty Upstream-Status: Submitted [https://lore.kernel.org/all/20230403111426.61327-2-andrejs.cainikovs@toradex.com/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-04-03colibri-imx8x: add usb supportAndrejs Cainikovs
Add USB support. Upstream-Status: Pending As of now, no iMX8 USB support present in mainline. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-03-07colibri-imx8x: construct fdtfile dynamicallyAndrejs Cainikovs
The following expression is used to construct the device tree name: fdtfile=${soc}-colibri-${fdt_board}.dtb - soc is set dynamically (either imx8qxp or imx8dx) - fdt_board can be modified by the user (eval-v3, aster, iris/iris-v2) Upstream-Status: Submitted [https://lore.kernel.org/all/20230303132642.15574-9-andrejs.cainikovs@toradex.com/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-03-07colibri-imx8x: extract is_imx8dx() from ram detectionMax Krummenacher
Refactor the detection of QXP vs. DX SoC into its own helper function. Upstream-Status: Submitted [https://lore.kernel.org/all/20230303132642.15574-8-andrejs.cainikovs@toradex.com/] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-03-07board: colibri-imx8x: add 2nd ethernet addressAndrejs Cainikovs
All Colibri iMX8X variants have 2nd RGMII on SoC, so add the address for 2nd ethernet. Upstream-Status: Submitted [https://lore.kernel.org/all/20230303132642.15574-2-andrejs.cainikovs@toradex.com/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-02-07board: verdin-imx8mp: change prints in spl_dram_init functionEmanuele Ghidoli
change prints to show which DDR configuration (single/dual rank) is used Upstream-Status: Pending Waiting for internal test and validation before sending to upstream. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-02-07board: verdin-imx8mp: compact slight different LPDDR4 configurationEmanuele Ghidoli
Deduplicate similar DDRC configurations and LPDDR4 training patterns by patching a single configuration. The aim is to reduce the SPL memory footprint and simplify maintenance of lpddr4_timing.c Upstream-Status: Pending Waiting for internal test and validation before sending to upstream. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-02-07board: verdin-imx8mp: update LPDDR4 configuration and trainingEmanuele Ghidoli
Update lpddr4 configuration and training using updated spreadsheet and tools from NXP using data from previous spreadsheet and verified toward datasheet: - MX8M_Plus_LPDDR4_RPA_v9.xlsx - mscale_ddr_tool_v3.30.exe From: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467 Some register values differ due to these fixes/modifications: - corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4) - corrected ECC related items, none of which affect normal operation when ECC is not enabled - corrected formula for calculation of tRTP in cell D122 Upstream-Status: Pending Waiting for internal test and validation before sending to upstream. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-02-07board: verdin-imx8mp: fix LPDDR4 refresh timingEmanuele Ghidoli
Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with current and futures memories. Fixes: 2bc2f817cea7 ("board: toradex: add verdin imx8m plus support") Upstream-Status: Pending Waiting for internal test and validation before sending to upstream. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-02-07board: verdin-imx8mp: update DDRC config to support different LPDDR4 memoriesEmanuele Ghidoli
Add support to Verdin IMX8MP V1.1B SKU which uses MT53E1G32D2FW-046 WT:B memory. Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on Verdin IMX8MP V1.0A it has 16 row addresses instead of 17. In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a 4 GB/rank memory. Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it is possible to have a single configuration working with both memories: - Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16 - New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16 With this change the memory space from the host processor is contiguous for both the configurations and the correct memory size is computed using get_ram_size() at runtime. Support for single rank memories still works thanks to the fact dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank memories. Related-to: ELB-5021 Upstream-Status: Pending Waiting for internal test and validation before sending to upstream. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
2023-01-19board: apalis-imx8: add 2nd ethernet addressAndrejs Cainikovs
All Apalis iMX8 variants have 2nd RGMII on SoC, so add the address for 2nd ethernet. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20230117142911.34257-1-francesco@dolcini.it/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-01-19apalis-imx8: add new 8gb wifi/bt som variantAndrejs Cainikovs
Add new SoM variant to existing ones. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20230113171751.331268-3-francesco@dolcini.it/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-01-19board: apalis-imx8: initialize snvsAndrejs Cainikovs
Initialize Secure Non-Volatile Storage, aka SNVS. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20230113171751.331268-20-francesco@dolcini.it/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-01-19board: apalis-imx8: add reset codeAndrejs Cainikovs
Add downstream specific iMX reset implementation. Upstream-Status: Inappropriate [other] This code uses sc_pm_reboot() which is not mainlined yet. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-01-19board: apalis-imx8: remove board_phy_config duplicateAndrejs Cainikovs
Remove a duplicate of weak board_phy_config() implementation in drivers/net/phy/phy.c. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20230113171751.331268-19-francesco@dolcini.it/] Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-01-19board: apalis-imx8: get rid of sc_err_t typePhilippe Schenker
sc_pm_setup_uart() returns int, not sc_err_t. Upstream-Status: Submitted [https://lore.kernel.org/u-boot/20230113171751.331268-18-francesco@dolcini.it/] (cherry picked from commit ecc0917dd4f7efd064a1b58f4f75b85478a794b3) Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2022-12-23apalis-imx8: update spdx license identifier stringMarcel Ziswiler
Update SPDX license identifier string. While at it also update copyright period. Upstream-Status: Submitted [https://lore.kernel.org/all/20221212000930.45505-11-marcel@ziswiler.com/] Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-12-23apalis-imx8: display build infoMarcel Ziswiler
Display build info with information about the version of SCFW, SECO and TF-A (ATF). Upstream-Status: Submitted [https://lore.kernel.org/all/20221212000930.45505-5-marcel@ziswiler.com/] Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-12-23apalis-imx8: turn off lcd backlight before OS handoverMarcel Ziswiler
U-Boot typically tears down the display controller before handing control over to Linux. On LCD displays disabling pixel clock leads to a fading out effect with vertical/horizontal lines. Make sure to disable back light GPIO Apalis BKL1 before booting Linux. Upstream-Status: Submitted [https://lore.kernel.org/all/20221212000930.45505-4-marcel@ziswiler.com/] Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-12-23apalis-imx8: implement pcb version and soc variant handlingMarcel Ziswiler
Implement PCB version and SoC variant handling which automatically loads the correct device tree for the Linux kernel. Upstream-Status: Submitted [https://lore.kernel.org/all/20221212000930.45505-3-marcel@ziswiler.com/] Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-12-23board: apalis-imx8: add new 8gb product variantPhilippe Schenker
Add the new Apalis iMX8 product variant 0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT the only difference to the product 0037 Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT is the 8gb of RAM. Toradex strategy to choose the correct RAM timing in SCFW is by fuses in the user area telling which RAM timing to load. This commit makes use of this information to set the correct size of the RAM and therefore distinguish between the new 0067 and 0037 product Upstream-Status: Backport [0da8dde6343fb91628794f9772b119bc7241c8a1] Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-15Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/imx_v2022.04: MA-20886 imx8ulp: Boot from recovery mode when pressing key
2022-11-15MA-20886 imx8ulp: Boot from recovery mode when pressing keyMaximus Sun
Make system enter recovery mode when user pressing "sw2" when i.MX 8ULP EVK and i.MX 8ULP EVK 9×9 board are powered on. Signed-off-by: Maximus Sun <maximus.sun@nxp.com> Change-Id: Ifc13c37fff4f6c7352161b6ad7d6014aeeafcc6d
2022-11-08Merge remote-tracking branch 'gh-nxp/lf_v2022.04' into ↵Philippe Schenker
update-to-5.15.52_2.1.0__toradex_imx_lf_v2022.04
2022-10-26Merge remote-tracking branch 'origin/ls_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/ls_v2022.04: LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd
2022-10-26LF-6627: nand drvier fixups in sdboot on ls1043ardb-pdWeiLu
Signed-off-by: WeiLu <w.lu@nxp.com>
2022-10-26Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/imx_v2022.04: LFU-426: qspihdr: Coverity Issue: unchecked return value MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name
2022-10-26MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file nameHan Xu
change the fdt file name with rpmsg postfix as the default. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-10-24Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/imx_v2022.04: LFU-428 imx8ulp: Add warning for CAAM non-secure state failure
2022-10-24LFU-428 imx8ulp: Add warning for CAAM non-secure state failureYe Li
When booting from OEM closed part, due to OTPMK not programmed correctly, CAAM is in non-secure state. Add a warning in SPL to indicate the problem to users. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-10-18Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/imx_v2022.04: LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check MLK-26034 imx6: Disable LCDIF clock before jumping to kernel
2022-10-18MLK-26034 imx6: Disable LCDIF clock before jumping to kernelYe Li
Disable LCDIF axi clock and pix clock CCGR before jumping to kernel to avoid potential MUX glitch issue on CSCDR2 LCDIF_PRE_CLK_SEL mux. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-10-18LF-6627: nand drvier fixups in nandboot on ls1043ardb-pdWeiLu
Signed-off-by: WeiLu <w.lu@nxp.com>
2022-10-18Merge remote-tracking branch 'origin/ls_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/ls_v2022.04: LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd
2022-10-14Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04BJ DevOps Team
* origin/imx_v2022.04: LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-02 05:34:16 +0000