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These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */
LSDMR2 0x0863B727 /* NORMAL */
LSDMR3 0x1863B727 /* MRW */
LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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These boards were meaning to deploy this value:
#define LCRR_DBYP 0x80000000
but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus
clock frequencies if the PLL is unable to lock. When in
PLL bypass mode, incoming data is captured in the middle
of the bus clock cycle. It is recommended that PLL bypass
mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an
override workaround.
In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these "count the zeros" problems, but
for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This enables the XGMAC ethernet driver and networking related config
options.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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As proposed by Mike Frysinger, mkdir can take more than one argument.
Instead of spawning two processes, create both the common and seaboard
directories in one go.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Now that we can set up the UART in common tegra code, make the boards
use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The clock init is not board specific, so move it into
the cpu code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This call is more of an architecture requirement than a board
one, so move it there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Seaboard changes have removed the need for common/board.o in the
Makefile. Propagate this change to the other Tegra2 builds.
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The Medcom is a 16:9 15" terminal that is used for patient infotainment
in hospitals.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The Plutux is a set-top box device based on the Tamonten processor
module. It can be connected to a display via an HDMI output.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Tamonten is an NVIDIA Tegra2-based SO-DIMM processor module that is
derived from the Harmony reference design.
Changes in v3:
* Remove unused gpio_config_uart().
* Remove call to tegra2_start().
* Use new tegra2_mmc_init().
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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On Seaboard the UART and SPI interfere with each other. This causes the UART
to receive spurious zero bytes after SPI transactions and also means that
SPI can corrupt a few output characters when it starts up if they are still
in the UART buffer.
This updates the board to use the SPI/UART switch to avoid the problem.
For now this feature is turned off since it needs changes to the NS16550
UART to operate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The Tegra2 Seaboard has the unfortunate feature that SPI and the console
UART are multiplexed on the same pins. We need to switch between one
and the other during SPI and console activity.
This new file implements a switch and keeps track of which peripheral
owns the pins. It also flips over the controlling GPIO as needed
Since we are adding a second file to board/nvidia/common, we create
a proper Makefile there and remove the direct board.o include from
board/nvidia/seaboard/Makefile
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This driver supports SPI on Tegra2, running at 48MHz.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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UARTB is used on some boards, so support it here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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UART selection is done with a lot of #ifdefs. This cleans things up
a little.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Use enable_gpmc_cs_config instead of local writing
timing configuration for GPMC.
Signed-off-by: Thomas Weber <weber@corscience.de>
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Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
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The twister board is a development board using
the TAM3517 SOM.
Support for NAND, 2 Ethernet (EMAC and SMC911),
USB (EHCI_OMAP).
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
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Fix the following checkpatch warning:
WARNING: braces {} are not necessary for single statement blocks
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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* 'next' of ../next:
mkenvimage: Add version info switch (-V)
mkenvimage: Fix getopt() error handling
mkenvimage: Fix some typos
phy: add Micrel KS8721BL phy definition
net: introduce per device index
mvgbe: remove setting of ethaddr within the driver
x86: Add support for specifying an initrd with the zboot command
x86: Refactor the zboot innards so they can be reused with a vboot image
x86: Add infrastructure to extract an e820 table from the coreboot tables
x86: Add support for booting Linux using the 32 bit boot protocol
x86: Clean up the x86 zimage code in preparation to extend it
x86: Import code from coreboot's libpayload to parse the coreboot table
x86: Initial commit for running as a coreboot payload
CHECKPATCH: ./board/esd/hh405/logo_320_240_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_1024_768_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/hh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/apc405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/voh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/voh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/hh405/fpgadata.c
CHECKPATCH: ./board/esd/pci405/fpgadata.c
CHECKPATCH: ./board/esd/tasreg/fpgadata.c
CHECKPATCH: ./board/esd/apc405/fpgadata.c
CHECKPATCH: ./board/esd/voh405/fpgadata.c
CHECKPATCH: ./board/esd/ash405/fpgadata.c
CHECKPATCH: ./board/esd/dasa_sim/fpgadata.c
CHECKPATCH: ./board/esd/ar405/fpgadata_xl30.c
CHECKPATCH: ./board/esd/ar405/fpgadata.c
CHECKPATCH: ./board/esd/plu405/fpgadata.c
CHECKPATCH: ./board/esd/wuh405/fpgadata.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405ab.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci4052.c
CHECKPATCH: ./board/esd/canbt/fpgadata.c
CHECKPATCH: ./board/esd/du405/fpgadata.c
CHECKPATCH: ./board/esd/cpciiser4/fpgadata.c
CHECKPATCH: ./board/dave/PPChameleonEVB/fpgadata.c
avr32:mmu.c: fix printf() length modifier
fat.c: fix printf() length modifier
cmd_sf.c: fix printf() length modifier
Make printf and vprintf safe from buffer overruns
vsprintf: Move function documentation into header file
Add safe vsnprintf and snprintf library functions
Move vsprintf functions into their own header
Conflicts:
tools/mkenvimage.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Since Ventana is derived from Seaboard and requires seaboard.c to build,
make sure board/nvidia/seaboard is created in the build tree.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Wolfgang Denk <wd@denx.de>
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Add a variable "toolchain" and configure the rootpath
for the nfsargs with this variable.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
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Fix:
misc.c: In function 'misc_init_r':
misc.c:119:3: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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Fix:
mv_eth.c: In function 'mv64360_eth_real_open':
mv_eth.c:425:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_stop':
mv_eth.c:643:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_xmit':
mv_eth.c:719:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_receive':
mv_eth.c:804:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_get_stats':
mv_eth.c:903:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_update_stat':
mv_eth.c:931:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable]
mv_eth.c:930:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'mv64360_eth_print_stat':
mv_eth.c:1012:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable]
mv_eth.c: In function 'eth_clear_mib_counters':
mv_eth.c:2069:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
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Fix:
universal.c: In function 's5pc210_phy_control':
universal.c:273:7: warning: 'ret' may be used uninitialized
in this function [-Wuninitialized]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
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GPIO configuration shall never be done inside a driver, never.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
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MACH_TYPE_TNY_A9G20 and MACH_TYPE_TNY_A9260 were removed
from mach-types.h. Add them to the board config file.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
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MACH_TYPE_SBC35_A9G20 was removed from mach-types.h.
Add it to the board config file.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
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During misc_init_r, make sure to setup the clocks
properly for the USB hub on the pandaboard. With
this in place, the USB hub and the ethernet works
on the pandaboard.
Signed-off-by: Chris Lalancette <clalancette@gmail.com>
Acked-by: Aneesh V <aneesh@ti.com>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Fix:
mx51evk.c:206:6: error: conflicting types for 'board_ehci_hcd_init'
/u-boot/include/usb/ehci-fsl.h:254:5: note: previous declaration of
'board_ehci_hcd_init' was here
We also fix board_ehci_hcd_init() for mx53loco board.
Building for mx53loco worked since <usb/ehci-fsl.h> is
not included here.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
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This change also forces the lib_sysinfo structure to be in the .data
section. Otherwise it ends up in the .bss section. U-boot assumes that it
doesn't need to copy it over during relocation, and instead fills that
whole section with zeroes. If we really were booting from ROM that would be
appropriate, but we need some information from the coreboot tables (memory
size) before then and have to fill that structure before relocation. We
skirt u-boot's assumption by putting this in .data where it assumes there
is still read only but non-zero data.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
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Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Roese <sr@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
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