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* implementation based on ti beagleboard/omap3evm
* timing data and i2c workaround for revision 0 boards taken from x-loader
* run-tested with overo revision 0 and 1 / boot from NAND and SDcard
* run-tested with x-loader
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
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This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Switch to the new EEPROM module and fix the problem of MAC address
being read from the wrong offset due to lack of distinction between
EEPROM layouts.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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Read revision from EEPROM and pass it to Linux.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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Add board specific EEPROM handling module,
read the serial number from the EEPROM and pass it to Linux.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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Move #ifdef CONFIG_SMC911X out of board_eth_init() function,
simplify the board_mmc_init() function, and enclose handle_mac_address()
in the CONFIG_SMC911X.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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this is for a prototyping board
vendor/product ids have been added to
http://elinux.org/BeagleBoardPinMux#List_of_Vendor_and_Device_IDs
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This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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Now the values in the defines agree with those in the manuals.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
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Add the initial support for Freescale i.MX6Q Sabre Lite board
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
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Remove 'all' target from Makefile, as this is unused code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Remove 'all' target from Makefile, as this is unused code.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Add initial support for Freescale MX28EVK board.
Tested boot via SD card and by loading a kernel via TFTP through
the FEC interface.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Let imx_get_mac_from_fuse function be a common function, so that other
mx28 boards can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.
This feature is important on mx28 SoC for example that has two FEC ports.
Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Bits 0 and 1 of CCM_CCGR7 are the usboh3 clock enable bits. Enabling this
clock is necessary for the USB download.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
CC: Jason Hui <jason.hui@linaro.org>
Acked-by: Jason Hui <jason.hui@linaro.org>
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This enable the network function on the i.mx6q armadillo2
board(arm2), thus we can use tftp to load image from network.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
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Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* 'master' of git://git.denx.de/u-boot-mpc85xx:
fsl_lbc: add printout of LCRR and LBCR to local bus regs
sbc8548: Fix up local bus init to be frequency aware
sbc8548: enable support for hardware SPD errata workaround
sbc8548: relocate fixed ddr init code to ddr.c file
sbc8548: Make enabling SPD RAM configuration work
sbc8548: Fix LBC SDRAM initialization settings
sbc8548: enable ability to boot from alternate flash
sbc8548: relocate 64MB user flash to sane boundary
Revert "SBC8548: fix address mask to allow 64M flash"
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
eXMeritus HWW-1U-1A: Minor environment variable tweaks
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* 'master' of git://git.denx.de/u-boot-ppc4xx:
board/mpl/pati: use the CFI driver for the PATI board
board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
board/mpl/pip405: use the CFI driver for the PIP405 board
board/mpl/common: remove the old legacy flash
ppc4xx: Setup HICB on Io64
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* 'master' of git://git.denx.de/u-boot-mpc83xx:
mpc8313erdb: fix mtdparts address
powerpc/83xx/km: add support for 8321 based tuge1 board
powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
powerpc/83xx/km: remove obsolete defines for tuda1
powerpc/83xx/km: update SDRAM parameters for km8321 boards
mpc8313erdb: Enable GPIO support on the MPC8313E RDB
mpc83xx: Add a GPIO driver for the MPC83XX family
gpio: Replace ARM gpio.h with the common API in include/asm-generic
gpio: Modify common gpio.h to more closely match Linux
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The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit. Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv. Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.
This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to
Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */
LSDMR2 0x0863B727 /* NORMAL */
LSDMR3 0x1863B727 /* MRW */
LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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These boards were meaning to deploy this value:
#define LCRR_DBYP 0x80000000
but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus
clock frequencies if the PLL is unable to lock. When in
PLL bypass mode, incoming data is captured in the middle
of the bus clock cycle. It is recommended that PLL bypass
mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an
override workaround.
In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these "count the zeros" problems, but
for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
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The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
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The new API no longer uses the extra cd parameter that was used to store
the card presence state. Instead, this information is returned via the
function's return value. board_mmc_getcd() returns -1 to indicate that
no card-detection mechanism is implemented; 0 indicates that no card is
present and 1 is returned if it was detected that a card is present.
The rationale for this change can be found in the following email
thread:
http://lists.denx.de/pipermail/u-boot/2011-November/110180.html
In summary, the old API was not consistent with the rest of the MMC API
which always passes a struct mmc as the first parameter. Furthermore the
cd parameter was used to mean "card absence" in some implementations and
"card presence" in others.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
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This enables the XGMAC ethernet driver and networking related config
options.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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As proposed by Mike Frysinger, mkdir can take more than one argument.
Instead of spawning two processes, create both the common and seaboard
directories in one go.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Now that we can set up the UART in common tegra code, make the boards
use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The clock init is not board specific, so move it into
the cpu code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This call is more of an architecture requirement than a board
one, so move it there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Seaboard changes have removed the need for common/board.o in the
Makefile. Propagate this change to the other Tegra2 builds.
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The Medcom is a 16:9 15" terminal that is used for patient infotainment
in hospitals.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The Plutux is a set-top box device based on the Tamonten processor
module. It can be connected to a display via an HDMI output.
Changes in v3:
* Remove unused implementation of gpio_config_uart().
* Implement MMC/SD card detection.
* Drop board_mmc_getcd() which is now implemented by common Tegra2
code.
* Add MAINTAINERS entry.
Changes in v2:
* No longer override the default CONFIG_SYS_TEXT_BASE setting.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Tamonten is an NVIDIA Tegra2-based SO-DIMM processor module that is
derived from the Harmony reference design.
Changes in v3:
* Remove unused gpio_config_uart().
* Remove call to tegra2_start().
* Use new tegra2_mmc_init().
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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On Seaboard the UART and SPI interfere with each other. This causes the UART
to receive spurious zero bytes after SPI transactions and also means that
SPI can corrupt a few output characters when it starts up if they are still
in the UART buffer.
This updates the board to use the SPI/UART switch to avoid the problem.
For now this feature is turned off since it needs changes to the NS16550
UART to operate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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