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2011-08-29Get hwid from GBB and correct write-protect GPIO polarityChe-Liang Chiou
BUG=none TEST=[ $(crossystem wpsw_boot) = 1 ] && [ crossystem hwid = "$HWID_YOU_ASSIGNED" ] Cherry-pick: 5f30788 Change-Id: Id29b56748fafc6ad64cd336207ac7ef43befbbf5 Reviewed-on: http://gerrit.chromium.org/gerrit/1004 Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29Implement cold rebootChe-Liang Chiou
The verified boot spec requires that firmware cold (not warm) reboots so that TPM gets reseted. BUG=chrome-os-partner:3574 TEST=manual 1. Run load_fw twice, and verify that SetupTPM failed in the second run ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... DEBUG: TPM: SetupTPM(r0, d0) ... DEBUG: TPM: SetupTPM() succeeded ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... DEBUG: TPM: SetupTPM(r0, d0) ... DEBUG: Unable to setup TPM and read stored versions. ------------------------------------------------------------ 2. Run load_fw twice and a reset in between, and results the same ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... CrOS> reset ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ------------------------------------------------------------ 3. Run load_fw twice and a "cros cold_reboot" in between, and verify that SetupTPM succeeds in both runs ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... CrOS> cros cold_reboot ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ------------------------------------------------------------ Cherry-pick: bbb6ba7 Change-Id: Ie74bb214c80714d1814b4ae295c4780aa2bc7ddc Reviewed-on: http://gerrit.chromium.org/gerrit/756 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
2011-08-29Remove TPM functions and x86-specific CPU stateChe-Liang Chiou
The removed TPM functions are implemented in verified boot reference library (vboot_reference), and so this commit removes the implementation of these functions in u-boot. This commit also removes codes that are related to x86-specific CPU state (S3 resume). BUG=none TEST=CROSS_COMPILE=armv7a-cros-linux-gnueabi- ./MAKEALL chromeos Cherry-pick: 75707bc Change-Id: Id4a967b9dd16549bb26adbe27ce96caa713bfe30 Reviewed-on: http://gerrit.chromium.org/gerrit/515 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29Fix compiler warnings on pmu.cJimmy Zhang
BUG=none TEST=Build and boot u-boot Change-Id: I20ad65d151312313bd8951cb6799c50e6e46840d Reviewed-on: http://gerrit.chromium.org/gerrit/2411 Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-08-29fdt: tegra2: Support USB config through FDTSimon Glass
This adds FDT configuration of USB ports. BUG=chromium-os:11623 TEST=Build and boot u-boot; usb start; network boot Change-Id: Ia3ea9f7ce816575dc0d99900a163d20e9cb65ecc Reviewed-on: http://gerrit.chromium.org/gerrit/2348 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-29tegra2: Tidy up USB implementationSimon Glass
This tidied up the USB configuration a little, to ready it for run-time configuration. BUG=chromium-os:11623 TEST=Build and boot U-Boot, usb start, network boot Change-Id: Ifdd5790c727cd697553455b57b167cd8dc51a823 Reviewed-on: http://gerrit.chromium.org/gerrit/2346 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-29Set vdd_core and vdd_cpu to highJimmy Zhang
At cold boot, the default voltage supplied by pmu is not high enough to support emc to run at its highest clock frequency. The code added here is to update the default vdd_core and vdd_cpu to higher values. BUG=none TEST=do cold and warm reboot and check the pmu output thru i2c commands i2c commands used to check vdd_core and vdd_cpu: Tegra2 (SeaBoard) # i2c dev 0 Setting bus to 0 Tegra2 (SeaBoard) # i2c md 34 20 0020: 00 00 00 10 10 07 17 17 07 13 13 00 00 00 00 13 Change-Id: Idd31a3f0ca39b31f142c4e96bf5a9b1b594f0d88 Reviewed-on: http://gerrit.chromium.org/gerrit/2257 Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-08-29fdt: Add USB definitionsSimon Glass
BUG=chromium-os:11623 TEST=Build U-Boot Change-Id: Id4f269e31b61d301ef6dce46cf6fea2ed3f95ed3 Reviewed-on: http://gerrit.chromium.org/gerrit/2345 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-29tegra2: Add LCD display driverSimon Glass
This adds basic LCD support for the Tegra2. BUG=chromium-os:13228 TEST=Build, boot on Seaboard Change-Id: Ib30a4e2fd1ba8e31d6bdf3f9d1d2bc70bef054ee Reviewed-on: http://gerrit.chromium.org/gerrit/1764 Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-29fdt: disable silent console by default on SeaboardSimon Glass
We don't want the Seaboard to use a silent console. This explicitly adds this option to the new config section of the device tree. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: I9735817f06beac6379bf1fe8bfe88dcde5fe70e3 Reviewed-on: http://gerrit.chromium.org/gerrit/963 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
2011-08-29tegra2: add i2c driverYen Lin
BUG=none TEST=exercise with i2c commands (i2c probe, md, mw) and access TPM Change-Id: I370185ffbd03ffd66cc9edf1ca2fce0b2689e739 Reviewed-on: http://gerrit.chromium.org/gerrit/1563 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-29Tidy up MMC to use to clock APISimon Glass
The MMC driver now uses the peripheral ID to identify which peripheral to use rather than the address of that peripheral. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard mmc part 0; ext2ls mmc 0:3 Change-Id: I42c09bca572349f2c9c2469959857d247a6a359f Reviewed-on: http://gerrit.chromium.org/gerrit/2035 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
2011-08-29Allow excluding reset handling code from u-boot.Gabe Black
BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Ib4ce184bf94e609d0e3e6b68389adec2fcbcf55e Reviewed-on: http://gerrit.chromium.org/gerrit/2153 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24Add a basic implementation for a coreboot board.Gabe Black
BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I56050d50cf2de0477907c6c79dc32aab59ae0622 Reviewed-on: http://gerrit.chromium.org/gerrit/2072 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24fdt: Add definitions for LCDSimon Glass
This adds definitions for the Tegra display controller and Seaboard LCD BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: Ia16358623f4cee81a17e420425f317ba5d274bdb Reviewed-on: http://gerrit.chromium.org/gerrit/1759 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24Add a dummy chromeos hardware layer for qemu emulation.Gabe Black
This implementation is strongly patterned after the ARM implementation. BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Idf2e56e7b5208a077821245630432936cf89f7ef Reviewed-on: http://gerrit.chromium.org/gerrit/2021 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24Move the SC520 specific pci.h header into an sc520 directory.Gabe Black
The arch/i386/include/asm/ic/pci.h header file include definitions which were not generic to i386 and where specifically for SC520. This change moves that header into a directory which more accurately reflects that. BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Icb4774f5c8d280904bbe1fa5cba42bdce002fcc0 Reviewed-on: http://gerrit.chromium.org/gerrit/2016 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24tegra2: Add clock and PLL control functionsSimon Glass
This adds functions for setting up clocks to peripherals, by selecting a parent clock and specifying a rate. BUG=chromium-os:13228 TEST=Build, boot on Seaboard Change-Id: I957723b5f0ef64244c16f44ae7cbd79abf06427d Reviewed-on: http://gerrit.chromium.org/gerrit/1290 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24Tegra2: Call power_det_init in board_initWei Ni
Call the power_det_init() in the board_init(). I missed it in the last CL. Bug=None TEST=Suspend seaboard by "echo mem > /sys/power/state", Probe C80 or C81 on seaboard to confirm that voltage is nearly zero. Change-Id: I15ea60660e5e9ae4d5a8a90da0eab5f259c1fe0f Signed-off-by: Wei Ni <wni@nvidia.com> Reviewed-on: http://gerrit.chromium.org/gerrit/1936 Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-08-24Tegra2: Turn off power detect in board initWei Ni
Tegra2: Turn off power detect in board init Tegra core power rail has leakage voltage around 0.2V while system in suspend mode. The source of the leakage should be coming from PMC power detect logic for IO rails power detection. That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' to PWR_DET (APBDEV_PMC_PWR_DET_0). BUG=None TEST=Suspend seaboard by "echo mem > /sys/power/state", Probe C80 or C81 on seaboard to confirm that voltage is nearly zero. Change-Id: I671e6b0bb6da8961892d04525ec6ef3604760c41 Signed-off-by: Wei Ni <wni@nvidia.com> Reviewed-on: http://gerrit.chromium.org/gerrit/1700 Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-08-24tegra2: Remove USB warningSimon Glass
BUG=chromium-os:13228 TEST=Build, check that warning goes away Change-Id: I4f4b74de00226964e31fb3ae02f360c4e8041779 Reviewed-on: http://gerrit.chromium.org/gerrit/1757 Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24tegra2: Rename CLOCK_PLL_ID_... to CLOCK_ID_...Simon Glass
It has become clear that this is a better name, since there is not really a distinction in the code between the two source clocks and the PLLs which are derived from them. BUG=chromium-os:13228 TEST=Build, boot on Seaboard Change-Id: I8e3a18d1fb767a6fd9af8a7d52f6cd0a97115a92 Reviewed-on: http://gerrit.chromium.org/gerrit/1755 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24Remove pre-relocation BSS variable access in uart-spi-fixSimon Glass
This was an unfortunate bug which has just shown itself. BUG=chromium-os:13228 TEST=Build, boot on Seaboard Change-Id: I29cabd81d941b4fca606f37aa5bb93d148a4d925 Reviewed-on: http://gerrit.chromium.org/gerrit/1756 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24mmc: Tegra2: add SD/MMC support for SeaboardTom Warren
SD cards in the RH slot (SDMMC3 controller) are seen OK internel eMMC chip (SDMMC4 controller) is seen OK ext2ls/ext2load work, fatls/fatinfo work, mmc cmds work (read, info, etc.) Card detect for SDIO3 on Seaboard is in place, but not called anywhere. CONFIG_SYS_NO_DCACHE is enabled to to cache coherency issues w/DMA. TBDs to be taken care of in the next phase. V2: Changed clock divisor and card clock divisor values based on 216MHz PLLP0 Added some comments as per Allen Martin's review V3: Added new pinmux_set_func calls in board.c Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=as above, on my T20-A03 Seaboard. U-boot.bin loaded via JTAG. Change-Id: I5955707034d41f7606ccf4cc99dd8ab5056c103e Reviewed-on: http://gerrit.chromium.org/gerrit/1745 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24Tegra2: Enable keyboard for seaboard configs.Rakesh Iyer
Enable keyboard for seaboard configs. BUG=None TEST=Keyboard works fine on Seaboard. Change-Id: I15342ad5de36e0d059870c98b5a403719b93b48c Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://gerrit.chromium.org/gerrit/1729 Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24fdt: tegra2: Enable console UART based on FDT selectionSimon Glass
When CONFIG_OF_CONTROL is defined, use the FDT rather than #define config options to determine which UART to enable (and use as the console) on start-up. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: I4b73707876629e1a53fee3d7924d4f6194207e88 Reviewed-on: http://gerrit.chromium.org/gerrit/959 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24fdt: Use device tree to provide SPI switch detailsSimon Glass
Rather than having the Seaboard SPI/UART switch in CONFIG options in the header files, use the device tree to configure this BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: If3b92b685b5fe31a97ef4bc3578a6aa00208d827 Reviewed-on: http://gerrit.chromium.org/gerrit/1661 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24fdt: tegra2: Add label for serial port 3Simon Glass
This adds a label to clean up the device tree ready for implementation of the SPI-UART switch using device tree. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: Id2dd7027bb562312d2c7c9023e1d7a24c7f86fbb Reviewed-on: http://gerrit.chromium.org/gerrit/1659 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24fdt: Add UART id numbers to support legacy codeSimon Glass
This adds a simple ID number to each UART, which is how the existing Tegra and NS16550 code addresses a UART. Ultimately this will not be needed, as the Tegra board.c code moves fully to device trees, and the NS16550 code can be adjusted. BUG=chromium-os:13875 TEST=Boot U-Boot on Seaboard and run kernel Change-Id: Iba6bc7b49ea9460637bd14c85a8748fb6612ddda Reviewed-on: http://gerrit.chromium.org/gerrit/1462 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24arm: tegra2: Refactor UART init to remove duplicated codeSimon Glass
This is a clean-up as well as allowing for run-time selection of UARTs more easily if required. It will be required for FDT. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: Ied483a2375ca753979829366d0495c056a77a1ab Reviewed-on: http://gerrit.chromium.org/gerrit/953 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24arm: tegra2: separate out SPI/UART switch code into its own fileSimon Glass
BUG=chromium-os:11623 TEST=build and boot U-Boot Change-Id: I1ac2ce58630b483a6d7a2388744e3bc983555bd1 Reviewed-on: http://gerrit.chromium.org/gerrit/617 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24tegra2: Add pinmux control functionsSimon Glass
This adds functions to change pinmux functions and the pullup/pulldown state for pin groups. BUG=chromium-os:11623 TEST=build and boot U-Boot on Seaboard Change-Id: I82130ede79c6c10420d81b90042d946afa7f1838 Reviewed-on: http://gerrit.chromium.org/gerrit/1642 Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24tegra2: Change PIN_ to PINGRPSimon Glass
PIN_ is a misnomer since the values actually represent groups of pins. BUG=chromium-os:13228 TEST=Build, boot on Seaboard Change-Id: I0362b76d39d80258c3d205d8189de639b8159432 Reviewed-on: http://gerrit.chromium.org/gerrit/1287 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24arm: tegra2: remove unneeded line from board MakefileSimon Glass
BUG=chromium-os:13875 TEST=Build, boot U-Boot on Seaboard Change-Id: Ibf6931e002fcc46a227a5f5854dfea7695617df2 Reviewed-on: http://gerrit.chromium.org/gerrit/616 Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24fdt: add initial device tree files for Tegra2Simon Glass
These files are from the device tree mailing list. So far they are very basic. BUG=chromium-os:11623 TEST=(none, this just adds files) Change-Id: I201110f58bf63e4b2d0728355cdfceb68455f0f0 Reviewed-on: http://gerrit.chromium.org/gerrit/618 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24arm: tegra2: Enable instruction cacheSimon Glass
Since low-level init is skipped, the instruction cache is never enabled on Tegra2. This explicitly calls this initialization as soon as the A9 is initialized. BUG=chromium-os:13875 TEST=Boot U-Boot on Seaboard and run kernel Change-Id: Ia617b2f7813a8ed5f05436117c9c4ab680229530 Reviewed-on: http://gerrit.chromium.org/gerrit/614 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24arm: tegra2: Use arch_cpu_init() to fire up Cortex-A9Simon Glass
We use board_early_init_f() for this but it is not really board init. Move to arch_cpu_init() instead. BUG=chromium-os:13228 TEST=Boot on Seaboard Change-Id: I36b0342700b19e073f4331cb1910c9d102d8b43b Reviewed-on: http://gerrit.chromium.org/gerrit/612 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Anton Staaf <robotboy@chromium.org>
2011-08-24Refactor firmware storage interfaceChe-Liang Chiou
Note: The implementation of SPI interface is empty here and is sent out in cl/6696066 to reduce the size of this CL. The following test results are conducted with cl/6696066. 1. Verify that bootstub can boot to rewritable firmware 2. Verify that refactoring does not break load_fw ------------------------------------------------------------ (Read firmware image from SPI flash) CrOS> sf probe 0 SF: Detected W25Q16B with page size 256, total 2 MiB 2048 KiB W25Q16B at 0:0 is now current device CrOS> sf read 0x01000000 0 0x00400000 (Test load_fw) CrOS> cros load_fw 0 0x01000000 0x00400000 0x10000000 LoadFirmware returns: LOAD_FIRMWARE_SUCCESS: firmware_index: 0 ------------------------------------------------------------ 3. Verify that refactoring does not break load_k ------------------------------------------------------------ (Following from previous command) (Insert Chrome OS image into SDCard slot) CrOS> mmc init 1 EMMC 1 Probed Successfully mmc1 is available CrOS> cros bootdev set mmc 1 Set boot device to mmc 1 0 (Test load_k) CrOS> cros load_k 0 0x10000000 SF: Detected W25Q16B with page size 256, total 2 MiB boot_flags: 0x00000004 shared_data_blob: 0x10000000 kernel_buffer: 0x027012f0 success: good kernel found on device kernel_buffer: 0x0040c000 partition_number: 2 bootloader_address: 0x736000 bootloader_size: 0x1000 partition_guid: fa e2 d2 39 82 ab 4b ff 93 b7 25 5e 88 a4 18 54 bytes_per_lba: 512 ending_lba: 0x003ce022 ------------------------------------------------------------ Change-Id: I12d24f8df2535a1cd58e120552431b9314224f6e R=robotboy@chromium.org,waihong@chromium.org BUG=none TEST=see above Review URL: http://codereview.chromium.org/6676109
2011-08-24Refactor firmware and kernel loaders to improve code sharingChe-Liang Chiou
The bootstub should output like the following: ------------------------------------------------------------ U-Boot 2010.09-00059-ga8a8981 (Mar 16 2011 - 14:00:35) Board: Tegra2 chromeos/tegra2/seaboard/stub DRAM: 1 GiB Using default environment In: tegra-kbc Out: lcd Err: lcd Hit any key to stop autoboot: 0 DEBUG: LoadFirmware started... DEBUG: Checking key block signature... DEBUG: Firmware 0 is valid. DEBUG: Checking key block signature... DEBUG: Will boot firmware index 0 ------------------------------------------------------------ The cros load_fw command should output like the following: (assume you load firmware image at [0x01000000:0x011d0000] ------------------------------------------------------------ CrOS> cros load_fw 0 0x01000000 0x001d0000 0x10000000 DEBUG: LoadFirmware started... DEBUG: Checking key block signature... DEBUG: Firmware 0 is valid. DEBUG: Checking key block signature... DEBUG: Will boot firmware index 0 LoadFirmware returns: LOAD_FIRMWARE_SUCCESS: firmware_index: 0 ------------------------------------------------------------ Type following command in developer firmware: (Assume that you inserted a Chrome OS SD card image) ------------------------------------------------------------ CrOS> mmc init 1 EMMC 1 Probed Successfully mmc1 is available CrOS> cros bootdev set mmc 1 Set boot device to mmc 1 0 CrOS> cros load_k 4 0x10000000 boot_flags: 0x00000004 shared_data_blob: 0x10000000 success: good kernel found on device kernel_buffer: 0x0040c000 partition_number: 2 bootloader_address: 0x736000 bootloader_size: 0x1000 partition_guid: fa e2 d2 39 82 ab 4b ff 93 b7 25 5e 88 a4 18 54 bytes_per_lba: 512 ending_lba: 0x003ce022 ------------------------------------------------------------ R=waihong@chromium.org BUG=None TEST=MAKEALL successfully and run commands above Review URL: http://codereview.chromium.org/6688063 Change-Id: Ia4f44a9de1703c7cef0f6b52d8bc951ff1cb81ee
2011-08-24Rename caller_internal_t to firmware_storage_tChe-Liang Chiou
Renaming the caller_internal_t for better reflecting its purpose. BUG=chromium-os:1302 TEST=MAKEALL successfully Review URL: http://codereview.chromium.org/6594066 Change-Id: I0e28c5934fdbd198ab4fdb278a33d4707767b3c6
2011-08-24Fix copyright statementChe-Liang Chiou
BUG=None TEST=None Review URL: http://codereview.chromium.org/6602003 Change-Id: I6dd474c1d111499db8940a8aea43045b6e4e00a6
2011-08-24Implement GPIO accessor functionsChe-Liang Chiou
BUG=chromium-os:10496 TEST=build successfully and run "cros test_gpio" in u-boot Review URL: http://codereview.chromium.org/6546014 Change-Id: I30ad04bef6a6fc4ac0dc9ff2c17a1087b18d9909
2011-08-24Factor out verified boot required hardware interfaceChe-Liang Chiou
BUG=none TEST=emerge-tegra2_seaboard chromeos-u-boot-next Review URL: http://codereview.chromium.org/6543034 Change-Id: I88dfd38aedd81281415ecb8156181a6cc4d46495
2011-08-24Fix Seaboard UART corruption on SPI activityTom Warren
On Seaboard the UART and SPI interfere with each other. This causes the UART to receive spurious zero bytes after SPI transactions and also means that SPI can corrupt a few output characters when it starts up if they are still in the UART buffer. This hack corrects this by making SPI record that it may have corrupted the UART, and making the UART take evasive action. BUG=chromium-os:13228 TEST=Try developer U-Boot on Seaboard, make sure it auto-boots OK now Review URL: http://codereview.chromium.org/6715017 Change-Id: If2281357f177eeb3a19a170ddea22adbcf5942e9 Reviewed-on: http://gerrit.chromium.org/gerrit/191 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24spi: Tegra2: Add SPI driver for SPIFLASH on SeaboardTom Warren
Change-Id: I306129ca7b8851639d7a062d877933e7c520c7ca Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://gerrit.chromium.org/gerrit/190 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-24Tegra2: Enable data cacheSimon Glass
This plumbs in support for the Cortex A9's data cache. Since armv7 instructions are used we need to ensure that none of these appear in the instruction stream executed by the ARM7TDMI. BUG=chromium-os:12253 TEST=build and boot U-Boot on Seaboard, check that it makes it to Linux Tegra2 (SeaBoard) # dcache Data (writethrough) Cache is ON Tegra2 (SeaBoard) # Change-Id: I91e6ef847abcb821dcaf482faa31d82b98ba93b8 Reviewed-on: http://gerrit.chromium.org/gerrit/198 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-24Tegra2: Add USB supportSimon Glass
This adds basic USB support for port 0. The other port is not supported by this CL. BUG=chromium-os:13875 TEST=Put USB stick in side port. Then: Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (gpt3) 2745808 bytes read Tegra2 (SeaBoard) # Change-Id: I10f9228377ee7ed7817bb30bf665d69c5e74f239 Review URL: http://codereview.chromium.org/6896012
2011-08-24Tegra2: Use clock and pinmux functions to simplify codeSimon Glass
BUG=chromium-os:13875 TEST=Build for Seaboard, boot Review URL: http://codereview.chromium.org/6899017 Change-Id: I6bb151ff353dba2192ab56a9db9ac9628133ec4e
2011-08-24Tegra2: add additional pin multiplexing featuresSimon Glass
This adds an enum for each pin and some functions for changing the pin muxing setup. BUG=chromium-os:13875 TEST=Build U-Boot for seaboard, boot Change-Id: Ic9b4b035cc0584d1391c0a8e3e4646fc532e8ec3 Review URL: http://codereview.chromium.org/6895010
2011-08-24Tegra2: Add more clock supportSimon Glass
This adds functions to enable/disable clocks and reset to on-chip peripherals. BUG=chromium-os:13875 TEST=build U-Boot for Seaboard, boot Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413 Review URL: http://codereview.chromium.org/6900006
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