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2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár
Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-13xilinx: common: Add support for SOC detectionMichal Simek
Code supports board detection based on information available in EEPROM in legacy or FRU format. But this is not enough for emulation and simulation systems which are lacking these identification EEPROMs. But SOC itself has normally registers for SOC identification. Based on them it is possible to compose detected name. That's why prepare infrastructure in common location for SOC platform detection which is called before board platform detection. SOC platform detection shouldn't detect real silicon and should fallback to current existing mechanism to identify boards based on EEPROMs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
2022-09-13arm64: xilinx: Move board_get_usable_ram_top() to common locationMichal Simek
The commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location") adds functionality for ZynqMP to read reserved memory node and do not place U-Boot to reserved location. This functionality is generic across all Xilinx SOCs that's why move it to common location to be used by all Xilinx SOCs. On zynq platform this is also fixing issue where U-Boot was placed to locating which was reserved already which ends up with error message "ERROR: reserving fdt memory region failed (addr=30000000 size=10000000 flags=4)" which is shown when bdinfo is called. Tested on vck190, zcu102, zc706 and kc705 to cover all platforms. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
2022-09-13xilinx: Define only mmc devnum not partitionMichal Simek
The commit 53b406369e9d ("DFU: Check the number of arguments and argument string strictly") added strict control over string that 0:1 partition definition is not valid anymore that's why use only device number without partition ID. Device is specified by 2nd parameter and partition by 3rd. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
2022-09-13xilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_infoMichal Simek
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME stores the name of firmware file to be loaded by SPL. Name can be selected via Kconfig that's why use the macro. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/601fbc2dfd16b4708fc6b5f86954e10add43334e.1660055571.git.michal.simek@amd.com
2022-09-13xilinx: Fix logic when dfu_alt_info is generatedMichal Simek
Generate dfu_alt_info only when it is not defined. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/464e4b325c644e52a660df9cf44eeb4d80427f6a.1660055571.git.michal.simek@amd.com
2022-09-12xilinx: zynqmp: Fix AES with a user provided keyJanne Ylalehto
The user provided key address was not flushed in struct aes because of the flushing location in the function. Signed-off-by: Janne Ylalehto <ylalehto@gmail.com> Link: https://lore.kernel.org/r/20220816124525.19671-1-ylalehto@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-07-26fpga: xilinx: add bitstream flags to driver descOleksandr Suvorov
Store a set of supported bitstream types in xilinx_desc structure. It will be used to determine whether an FPGA image is able to be loaded with a given driver. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-07-26xilinx: common: Use strlcpy instead of strncpyMichal Simek
It is recommendation done by checkpatch to all the time have \0 terminated strings. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c7bfab50c40f6213f1b347b5e4674e382e83cb94.1658413156.git.michal.simek@amd.com
2022-07-26xilinx: Wire uuid reading from FRUMichal Simek
UUID is already recorded when FRU is parsed but it is not copied to local structures and exported to variable that's why simply add it. Data is saved in binary format but there must be conversion to string for exporting it to variable and string should be in uuid format too. One way how to use it directly is to setup pxeuuid based on it. For example via preboot with "setenv pxeuuid ${board_uuid}" Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1dfa4b4220a508abc05351da2119880811b77612.1658413156.git.michal.simek@amd.com
2022-07-26zynqmp: Run board_get_usable_ram_top() only on main U-BootAshok Reddy Soma
With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location"), the function board_get_usable_ram_top() is allocating MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this much memory in case of mini U-Boot. Keep these functions which use lmb under CONFIG_LMB so that they are compiled and used only when LMB is enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Move helper functions below header includesStefan Herbrechtsmeier
Move helper functions in psu_init files below header includes to avoid forward declarations. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-15-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: make spi flash support optionalStefan Herbrechtsmeier
The set_dfu_alt_info function use the CONFIG_SYS_SPI_U_BOOT_OFFS define to set the dfu_alt_info environment variable for qspi boot mode. Guard the usage of CONFIG_SYS_SPI_U_BOOT_OFFS to make spi flash support optional. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-11-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: common: Separate display cpu info functionStefan Herbrechtsmeier
Move the print_cpuinfo function of CONFIG_DISPLAY_CPUINFO into its own source file to support reuse by other board vendors. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-10-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: cpuinfo: Print soc machineStefan Herbrechtsmeier
Print the soc machine in the print_cpuinfo function. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-9-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24soc: xilinx: zynqmp: Add machine identification supportStefan Herbrechtsmeier
Add machine identification support based on the zynqmp_get_silicon_idcode_name function and use the soc_get_machine function of the soc uclass to get silicon idcode name for the fpga init. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Merge device listsStefan Herbrechtsmeier
Merge the svd / xck devices into to the common zynqmp device list. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-6-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Reuse shift macros to define masksStefan Herbrechtsmeier
Reuse the shift macros to define the masks. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-5-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Add macro for device type maskStefan Herbrechtsmeier
Add a macro for the device type mask of the id code. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-4-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24xilinx: zynqmp: Replace strncat with strlcatStefan Herbrechtsmeier
Replace strncat with strlcat to always produce a valid null-terminated string. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-3-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: add support for handling PVR dataOvidiu Panait
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: Kconfig: introduce XILINX_MICROBLAZE0_FPGA_FAMILY optionOvidiu Panait
Provide a static Kconfig value for the target FPGA archtitecture, as it is done in Linux. The cpu-uclass driver will cross-check it with the value read from PVR10 register. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce Kconfig options for icache/dcache sizesOvidiu Panait
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2022-06-24microblaze: cache: improve icache Kconfig optionsOvidiu Panait
Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve dcache Kconfig optionsOvidiu Panait
Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24arm64: versal: Add support to load an app at EL1Ashok Reddy Soma
Add support to switch to EL1 and load an EL1 app from U-Boot which is executing at EL2 or EL3 in aarch64 mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220506055345.1921-1-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-06xilinx: fru: Replace spaces with \0 in detected revisionMichal Simek
Also fix board revision field where spaces are used instead of \0. The same change was done for board name by commit 530560b6f8eb ("xilinx: fru: Replace spaces with \0 in detected name"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e069e5134e57899e859786ad8ba48721df6df752.1653911444.git.michal.simek@amd.com
2022-05-18arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configurationNeal Frager
This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) - DP system time clock PLL should use RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Register 0xFD1A007C configures the DP system time clock PLL. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
2022-05-18arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configurationNeal Frager
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu102-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com
2022-05-18arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configurationNeal Frager
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com
2022-05-18arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configurationNeal Frager
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com
2022-05-13xilinx: Handle board_get_usable_ram_top(0) properlyMichal Simek
board_get_usable_ram_top() was designed for getting the top most location for U-Boot allocation that's why function itself supports via total_size parameter to find out where the right location for U-Boot is. But function itself is also reused by different (EFI) which is passing total_size as 0 to find out where the usable ram top is. For this case doesn't make sense (a waste time) to call any lmb functions. That's why simply return gd->ram_top. And gd->ram_top is filled already based on previous call for U-Boot iself. The same solution is also used by stm32mp by commit 92b611e8b003 ("stm32mp: correctly handle board_get_usable_ram_top(0)") and commit c8510e397fad ("stm32mp: Fix board_get_usable_ram_top()"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com
2022-04-21xilinx: versal: board: use CONFIG_COUNTER_FREQUENCYPeng Fan
Since versal has CONFIG_COUNTER_FREQUENCY, so use it. And COUNTER_FREQUENCY will be dropped. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2022-04-19.mailmap: Start to use new amd.com email addressMichal Simek
Xilinx has been acquired by AMD that's why emails should be also updated. The patch is updating .mailmap file and also MAINTAINERS files as was done by commit 5cd1ecb99490 ("ppc: qemu: Update MAINTAINERS for correct email address"). The rest of my emails are not going to change. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-04-15capsule: board: Add information needed for capsule updatesSughosh Ganu
Add a structure which defines the information that is needed for executing capsule updates on a platform. Some information in the structure like the dfu string is used for making the update process more robust while some information like the per platform image GUIDs is used for fixing issues. Initialise this structure in the board file, and use the information for the capsule updates. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2022-04-05arm64: zynqmp: Record ID code for XCZU1EG deviceMichal Simek
Add ID code for 1eg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5b6c9f6a25bba076f304bc4699f6f676a929a683.1648619516.git.michal.simek@xilinx.com
2022-03-29arm64: zynqmp: Remove low level UART setting contMichal Simek
There is no reason to do serial initialization. Uart driver does it already based on DT. Good effect is that it is clear which interface is console. The same change was done in past by commit 84d2bbf082fa ("arm64: zynqmp: Remove low level UART setting"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/91a73f292bafc4b64ed09954cc23780496da4b65.1648125082.git.michal.simek@xilinx.com
2022-03-29arm64: versal: Do not place u-boot to reserved memory locationMichal Simek
Versal can also have reserved space in DT which u-boot has to avoid to placing self to that location. The same change was done in ZynqMP by commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location") and also for microblaze by commit d7b5cc89d329 ("microblaze: Do not place u-boot to reserved memory location"). The patch was tested by adding reserved-memory node to DT and check via bdinfo back. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/15426fa6d64835dd23c5c8c12bbfc97306fb6098.1647527129.git.michal.simek@xilinx.com
2022-03-09arm64: zynqmp: add support for zcu106 rev1.0Neal Frager
This patch adds psu_init for Xilinx ZCU106 rev1.0. Xilinx ZCU106 rev1.0 has newer x16 DDR4 memories and it is SW compatible with revA. Signed-off-by: Neal Frager <neal.frager@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/997b3e23457e4d24ce0e197d742382aaec36c2b2.1646230318.git.michal.simek@xilinx.com
2022-03-07microblaze: Do not place u-boot to reserved memory locationMichal Simek
Microblaze can also have reserved space in DT which u-boot has to avoid to placing self to that location. The same change was done in Zynqmp by commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location"). This feature was tested with this memory description on kc705: memory { device_type = "memory"; reg = <0x80000000 0x40000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; alloc@b00000000 { reg = <0xb0000000 0x10000000>; no-map; }; alloc@a8000000 { reg = <0xa8000000 0x00010000>; no-map; }; }; And in U-Boot log you can check u-boot relocation address and reserved locations. U-Boot 2022.01-03974-gb1b4c2dea9b9 (Feb 25 2022 - 11:59:48 +0100) Model: Xilinx MicroBlaze DRAM: 1 GiB Flash: 128 MiB Loading Environment from nowhere... OK In: serial Out: serial Err: serial Model: Xilinx MicroBlaze Net: AXI EMAC: 40c00000, phyaddr 7, interface gmii eth0: ethernet@40c00000 U-BOOT for microblaze-generic U-Boot-mONStR> bdi ... DRAM bank = 0x00000000 -> start = 0x80000000 -> size = 0x40000000 ... relocaddr = 0xaff69000 ... lmb_dump_all: memory.cnt = 0x1 memory[0] [0x80000000-0xbfffffff], 0x40000000 bytes flags: 0 reserved.cnt = 0x3 reserved[0] [0xa8000000-0xa800ffff], 0x00010000 bytes flags: 4 reserved[1] [0xafe87bb0-0xafffffff], 0x00178450 bytes flags: 0 reserved[2] [0xb0000000-0xbfffffff], 0x10000000 bytes flags: 4 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/ea0a8ccce723478eb518f6fdceb91d4f129efb68.1646122398.git.michal.simek@xilinx.com
2022-03-07Revert "board: zynqmp: Fix for wrong AMS setting by ROM"T Karthik Reddy
This reverts commit dfbe492edef421de09617dc26805fc428440924e. Analog bus control register should be programmed in SPL only. This commit 3414712ba8a ("arm64: zynqmp: Writing correct value to ANALOG_BUS") is programming the same. So revert this commit. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/215bc936e36f88d2e7c4422ec68cad6d40cb8f68.1645624892.git.michal.simek@xilinx.com
2022-03-07fru: ops: Add support to read mac addresses from multirecordAshok Reddy Soma
Add support to read MAC addresses from mac address multirecord. Check if multi record is found, then jump to mac address multirecord by comparing the record type field. If it matches mac address multirecord(0xD2), then copy mac addresses. Copy these read MAC address in xilinx_read_eeprom_fru so that they are updated to eth*addr in board_late_init_xilinx(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/18f31bc528820934854ea5fd9dc581778fc1e40c.1645624855.git.michal.simek@xilinx.com
2022-03-07xilinx: common: Optimise updating ethaddr from eepromAshok Reddy Soma
In board_late_init_xilinx() eth*addr are updated from the values read from eeprom. Ideally the MAC addresses are updated sequencially. So if any MAC address is invalid, it means there are no further valid values. So optimise this logic by replacing continue with break. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/efef0d07add5d5777396ea111ad75411dc402db3.1645624855.git.michal.simek@xilinx.com
2022-03-07fru: ops: Return error from checksum if data is all zero'sAshok Reddy Soma
fru_checksum function is simply adding all the bytes and returning the sum. If the data passed to this function is all zero's then it will return 0, and the functions calling this api will assume that checksum is correct. Ideally this is not good. Fix this by returning error if all the data is 0's. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/ac0366fe55c60a818a3f9ed33d96826c817d5520.1645624855.git.michal.simek@xilinx.com
2022-03-07fru: ops: Clear fru table before storing dataAshok Reddy Soma
Fill fru table with 0's before using it, to avoid junk data. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/e5f15caf9c2102316e39f300d7c9c1ecb6be8439.1645624855.git.michal.simek@xilinx.com
2022-02-21arm64: zynqmp: Fix debug uart initializationMichal Simek
The commit 0dba45864b2a ("arm: Init the debug UART") calls debug_uart_init() from crt0.S but it won't work because SOC is not configured yet. That's why create board_debug_uart_init() which calls psu_init() via new psu_uboot_init() earlier before the first access to UART in SPL. In full U-Boot call psu_uboot_init() only when CONFIG_ZYNQMP_PSU_INIT_ENABLED is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/878dc2daaa8685346f889989fbfb98b2e44da7fb.1645104518.git.michal.simek@xilinx.com
2022-02-21ARM: zynq: Fix debug uart initializationMichal Simek
The commit 0dba45864b2a ("arm: Init the debug UART") calls debug_uart_init() from crt0.S but it won't work because SOC is not configured yet. That's why create board_debug_uart_init() which calls ps7_init() earlier before the first access to UART. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/18e67e02a0c7190839a1ef3a11f3fd6babcf34cc.1645104518.git.michal.simek@xilinx.com
2022-02-21arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLEDMichal Simek
ZYNQMP_PSU_INIT_ENABLED is called only when BOARD_EARLY_INIT_F is defined that's why cover this dependency in Kconfig. board_early_init_f() is only part related to CONFIG_ZYNQMP_PSU_INIT_ENABLED which is disabled now that's why disable BOARD_EARLY_INIT_F and also build board_early_init_f() only when CONFIG_BOARD_EARLY_INIT_F is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d89253ec1590cd513dcd4bfbedebae618bd6d605.1645104518.git.michal.simek@xilinx.com
2022-02-21xilinx: Enable OF_BOARD for zynq and zynqmp boardsMichal Simek
The commit 985503439762 ("fdt: Don't call board_fdt_blob_setup() without OF_BOARD") forced to enable OF_BOARD for platforms which provide DT externally. Zynq/ZynqMP boards are using this feature for a long time that's why there is a need to enable it by default. Also code expects to return error in case of error that's why also fill it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/9f11bbffe2849f4da7d72712082d579262fe8fd8.1645104518.git.michal.simek@xilinx.com
2022-02-15microblaze: exception: migrate MICROBLAZE_V5 to KconfigOvidiu Panait
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only covers delay slot exception support. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-2-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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