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2011-10-17CHROMIUM: Clean up cros gpio codeSean Paul
This CL simplifies how cros gpios are handled by moving the required logic out of cros_gpio.c and into the application logic. This means that cros_gpio.c assumes that none of the gpios are required, and just returns an error when fetch is called. It's up to the caller of fetch to determine whether or not they should ignore the error or act upon it. BUG=chromium-os:21700 TEST=Tested on asymptote, ensured gpio access worked as expected. Change-Id: Ief3f1915026bfe981d345b9cc4709fef19edc7bf Signed-off-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10174 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-14CHROMIUM: ARM: tegra: Add default values for power and lid switch gpiosSean Paul
Add default values for the power and lid switches such that a dts file can exclude them and not suffer from immediate shutoffs and spam on boot. Also remove the lid switch from seaboard dts file since it is not relevant on that platform. BUG=chrome-os-partner:6027,chromium-os:17062 TEST=Tested on asymptote and seaboard Change-Id: I0bec112af345f7bef4cfbdc7cb44c0017cfecad3 Signed-off-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10037
2011-09-13tegra: Rename is_tegra2_processor_resetSimon Glass
Change tegra2 to tegra to make it more generic. BUG=chromium-os:19004 TEST=build and boot on Seaboard Change-Id: Iad6de3bb6cc6031167862054b78a57f66dea9cd5 Reviewed-on: http://gerrit.chromium.org/gerrit/7127 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-09-09tegra: Rename tegra2.h to tegra.hSimon Glass
We want to move to the idea of drivers and boards using generic tegra include files, and have these include files deal with the tegra2/3 differences. This will make it easier to share code between tegra2/3. BUG=chromium-os:19004 TEST=build and boot on Seaboard Change-Id: I9c4eec30707e41678fb307982a34fe383694ba16 Reviewed-on: http://gerrit.chromium.org/gerrit/7000 Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-29CHROMIUM: decode GPIO configs through <&gpio ...>Che-Liang Chiou
cros_gpio module used a ad-hoc format of GPIO config, and it should use <&gpio ...> instead. This patch changes the format of GPIO config. Note: In between calls to gpio_direction_input() (in fdt_setup_gpio()) and calls to gpio_get_value(), you have to insert a small delay if the input source is connected to the GPIO through a sufficiently large series resister (say, 200K ohm) so that the RC time constant for charging the gate capacitance on the input is non-trivial. As a matter of fact, I tested on Kaen and Aebl, and found only write protect GPIO needs this delay, and the delay time is less than 10 us. And we may safely hide this delay by decoupling the initialization and reading of GPIOs. BUG=none TEST=Run "vboot_test gpio" on Kaen and Aebl, and check GPIO readings TEST=Run "crossystem" on Kaen and Aebl after boot, and check GPIO readings Change-Id: Ib4d93c2ce156eb09ffc24a3882f83490d25c1e91 Reviewed-on: http://gerrit.chromium.org/gerrit/5726 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29Revert "Make the FMAP configuration decoding function board specific."Gabe Black
This reverts commit 23cefdce356de66442d858abf12c72afc8d33cac. Since we changed our minds about loading FMAP information from CBFS, we can go back to using the same mechanism on ARM and x86. BUG=chrome-os-partner:5432 TEST=Built and booted on x86-alex and verified that the FMAP information showed up in debugging output from vboot_twostop. Change-Id: Id41c82ca24dbfa301559e24104b5e226ec9b7e03 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/5864 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Make the FMAP configuration decoding function board specific.Gabe Black
This change makes the FMAP configuration decoding function board specific so that it can, for instance, use CBFS to store the FMAP on x86. The ARM implementation uses fdt_decode_twostop_fmap in its implementation and should behave the same. The new more generic interace is called decode_twostop_fmap. BUG=chrome-os-partner:5248 TEST=Built, installed and booted on Kaen, built and installed on Alex, ran vboot_twostop and saw new "unimplemented" message. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I07f6f8f7c8a62c5998ec4919d4609a7ac84783da Reviewed-on: http://gerrit.chromium.org/gerrit/5233 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Remove the device tree from one of the vboot support APIs.Gabe Black
This change removes the device tree from one of the vboot support APIs so that they fit better with coreboot u-boot. Specifically this is cros_gpio_fetch which is for getting GPIO values. Coreboot will read these and provide the values through its coreboot tables. The device tree pointer is global data so it doesn't need to be passed around as a parameter to be accessible. This change also removes the device tree from other interfaces in cmd_vboot_twostop.c so the structure of the code is more consistent. This way people can expect the device tree to always be the one pointed at by the global data and not sometimes one and sometimes the other, even though as written those will be equivalent. This change also takes the opportunity to mark the local functions in that file static, which is most of them. BUG=chrome-os-partner:4552 TEST=Built for x86-alex and tegra2_kaen. Installed and booted to chromeos login on Kaen. Change-Id: I084e774d97025d9ec71abe09c92fab8a7827892f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/5232 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29CHRIMIUM: aebl: kaen: seaboard: implement machine power offChe-Liang Chiou
This patch is derived from kernel's seaboard power management driver and tps6586x regulator driver. BUG=chrome-os-partner:4738 TEST=press power button or close lid in dev and rec mode Change-Id: I285856b52dcaba6ba3c29cacf47a8c592fbe3256 Reviewed-on: http://gerrit.chromium.org/gerrit/4922 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: Fix warning when cros-debug is off.Tom Wai-Hong Tam
The warning is unused variable. BUG=none TEST=build without error: USE="-cros-debug" emerge-tegra2_aebl chromeos-u-boot Change-Id: I7315ca9d802826bee132525668d7e1f686ed4786 Reviewed-on: http://gerrit.chromium.org/gerrit/4723 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29CHROMIUM: rename is_cold_boot to is_processor_resetChe-Liang Chiou
The predicate function is_cold_boot() is in fact telling you whether we are booting from a processor reset. BUG=chrome-os-partner:5100 TEST=build cleanly Change-Id: I70f56448dd1b327426cf759854c35e20e0b4cfcf Reviewed-on: http://gerrit.chromium.org/gerrit/4644 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: move VbExNvStorageRead/Write to board-specific directoryChe-Liang Chiou
As ARM accesses non-volatile storage from eMMC and x86 from CMOS, the accessor functions that export to vboot_reference are really not board-independent and so should be put at a board-dependent module. BUG=none TEST=make Change-Id: Idbd4d70372770597aa8897524ee6a1ffe173bfea Reviewed-on: http://gerrit.chromium.org/gerrit/4646 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29CHROMIUM: Add lid_open switch and power_key switch to fdt and add a testTom Wai-Hong Tam
BUG=chrome-os-partner:4738 TEST=build without error, run "vboot_test gpio" on Aebl Tegra2 # vboot_test gpio cros_gpio: wpsw : port= 59, polarity=0, value=1 cros_gpio: recsw : port= 56, polarity=0, value=0 cros_gpio: devsw : port=168, polarity=1, value=0 cros_gpio: lidsw : port= 23, polarity=0, value=1 cros_gpio: pwrsw : port=170, polarity=0, value=0 --- Pressed the power key --- Tegra2 # vboot_test gpio cros_gpio: wpsw : port= 59, polarity=0, value=1 cros_gpio: recsw : port= 56, polarity=0, value=0 cros_gpio: devsw : port=168, polarity=1, value=0 cros_gpio: lidsw : port= 23, polarity=0, value=1 cros_gpio: pwrsw : port=170, polarity=0, value=1 --- Closed the lid --- Tegra2 # vboot_test gpio cros_gpio: wpsw : port= 59, polarity=0, value=1 cros_gpio: recsw : port= 56, polarity=0, value=0 cros_gpio: devsw : port=168, polarity=1, value=0 cros_gpio: lidsw : port= 23, polarity=0, value=0 cros_gpio: pwrsw : port=170, polarity=0, value=0 Change-Id: Ib9fe188f39e266f806a823e694d8ea0867a8ef19 Reviewed-on: http://gerrit.chromium.org/gerrit/4485 Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29CHROMIUM: remove codes based on deprecated API of vboot_referenceChe-Liang Chiou
vboot_reference is redesigned and deprecates parts of its API. This patch remove those U-Boot integration codes that are based on the deprecated API. BUG=none TEST=clean build okay Change-Id: I45e08b8f5b6cec8f1bd62e760361f169aac4b687 Reviewed-on: http://gerrit.chromium.org/gerrit/4382 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29CHROMIUM: refactor checking cold boot interfaceChe-Liang Chiou
BUG=chromium-os:17424 TEST=boot on Seaboard Change-Id: I103c7060ed37c340e173498cfa70cf3493b2c503 Reviewed-on: http://gerrit.chromium.org/gerrit/4000 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: refactor GPIO interfaceChe-Liang Chiou
BUG=chromium-os:17424 TEST=boot on Seaboard Change-Id: I9b1f42801eedfba5e7f4e85a5b3ac1e1c106b6bf Reviewed-on: http://gerrit.chromium.org/gerrit/3998 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: twostop: cleanup config flagsChe-Liang Chiou
The variants of Chrome OS verified boot are: * chromeos_seaboard_onestop implements twostop firmware based on prior-redesigned vboot_reference. It is called onestop because it was implementing onestop boot. * chromeos_seaboard_vboot implements ordinary verified boot, which has bootstub, recovery, normal, and developer firmware, based on redesigned vboot_reference. * chromeos_tegra2_twostop implements twostop firmware based on redesigned vboot_reference. This variant is going to replace chromeos_seaboard_onestop. We split config flags into: * CONFIG_CHROMEOS enables codes that are shared among all variants. * CONFIG_CHROMEOS_VBEXPORT enables codes that implements APIs defined in vboot_api.h. * CONFIG_CHROMEOS_{ONESTOP,TWOSTOP,VBOOT} enables codes that are specific to each variant. Note that we would further cleanup or reorganize config flags after we migrate from chromeos_seaboard_onestop to chromeos_tegra2_twostop. BUG=chromium-os:17424 TEST=build cleanly Change-Id: I7574ec9376047693065b4295edb85b65acb4ea37 Reviewed-on: http://gerrit.chromium.org/gerrit/3943 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
2011-08-29CHROMIUIM: add gpio port number to crossystem dataChe-Liang Chiou
BUG=none TEST=boot and see gpio port number are set properly Change-Id: Ib4dbd54d7a50b6e31fb90c2c1977babab5f7b78b Reviewed-on: http://gerrit.chromium.org/gerrit/3670 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
2011-08-29CHROMIUM: fdt: add gpio polarity to fdt and crossystem dataChe-Liang Chiou
The raw gpio readings are not the logical values of true/false. A gpio may connect to device that is either high active or low active. That is, a raw reading of 1 from low active device actually means "false". In this context, we refer to this as a gpio's polarity. Note that a gpio polarity may differ board by board, depending on the actual wiring of the board. The u-boot and the crossystem (a user space program) needs the polarities to correctly interpret the raw gpio readings. The crossystem needs polarities for the gpio values in the crossystem data blob that u-boot passes to kernel (these values are "post-interpretation"). Instead, the crossystem is required to read "current" raw gpio readings and interpret these readings to a user. Note: I merely copied polarity configuration to kaen and aebl, but I did not test its correctness. BUG=chromium-os:16508 TEST=boot on Seaboard 1. Turn on Seaboard with dev switch on and rec switch off 2. Check debug output of u-boot ---------------------------------------- cros_onestop_firmware: polarity: cros_onestop_firmware: - wpsw: 1 cros_onestop_firmware: - recsw: 0 cros_onestop_firmware: - devsw: 1 cros_onestop_firmware: gpio value: cros_onestop_firmware: - wpsw: 1 cros_onestop_firmware: - recsw: 0 cros_onestop_firmware: - devsw: 1 ---------------------------------------- 2. Check /proc/device-tree/crossystem/ ---------------------------------------- $ od -x polarity_write_protect_sw 0000000 0000 0100 0000004 $ od -x polarity_recovery_sw 0000000 0000 0000 0000004 $ od -x polarity_developer_sw 0000000 0000 0100 0000004 ---------------------------------------- Change-Id: Ie92c31ce0abddf0271e73669b429621deaed76dd Reviewed-on: http://gerrit.chromium.org/gerrit/3650 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: twostop: prototype twostop firmwareChe-Liang Chiou
We modify onestop firmware to support twostop booting. Basically we only implemented R/W firmware verification. TODO * Read R/W firmware from mmc * Set main R/W firmware A or B in crossystem data * Read TPM's firmware version BUG=chromium-os:17056 TEST=boot r/w firmware on seaboard Change-Id: I77657547a2eafd1f7a4dafade26911cf1cc069b0 Reviewed-on: http://gerrit.chromium.org/gerrit/3603 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29CHROMIUM: [6/7] fix to merely compilable; rewrite gpio accessor to the new ↵Che-Liang Chiou
tegra gpio dirver This is the sixth of the seven commits in the series. For more information, please refer to the first commit. Changes in this commit: * rewrite gpio accessor to the new tegra gpio dirver BUG=chromium-os:16508 TEST=manual; see the first commit Change-Id: Ib478e2b4f9f35b86acb067e7c35fde725e57f056 Reviewed-on: http://gerrit.chromium.org/gerrit/2680 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-29CHROMIUM: [1/7] fix to merely compilable; delete obsolete filesChe-Liang Chiou
The compiler warnings and errors due to cherry-picking verified boot integration library into new u-boot codebase are fixed here. This and the following six commits only give you a compilable repository, and do not give you a working verified boot; neither onestop nor the old four-variants style of verified boot are supposed to be functioning. Changes in this commit: * delete obsolete files: - cpu_state.c - eeprom_driver.c * delete unused firmware storage device: - firmware_storage_{nand,ram}.c BUG=chromium-os:16508 TEST=manual After all seven commits are checked in, you should be able to run: make ARCH=arm \ CROSS_COMPILE=armv7a-cros-linux-gnueabi- \ USE_PRIVATE_LIBGCC=yes \ VBOOT=/build/tegra2_seaboard/usr \ chromeos_seaboard_onestop_config make ARCH=arm \ CROSS_COMPILE=armv7a-cros-linux-gnueabi- \ USE_PRIVATE_LIBGCC=yes \ VBOOT=/build/tegra2_seaboard/usr \ all Change-Id: I8a73e5536277a7c22dad3f95c1a33da90689a6f3 Reviewed-on: http://gerrit.chromium.org/gerrit/2676 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-29can separately enable vboot-related debug outputChe-Liang Chiou
U-Boot debug output is very verbose, and sometimes does not help debugging verified boot related changes. This commit let us enable vboot-related debug output separately. BUG=chromium-os:15747 TEST=boot and see vboot-related debug output Cherry-pick: 84c65f7 Change-Id: I934d46654777347f09d9d3d71c55b3e478fd02c6 Reviewed-on: http://gerrit.chromium.org/gerrit/1532 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-29Get hwid from GBB and correct write-protect GPIO polarityChe-Liang Chiou
BUG=none TEST=[ $(crossystem wpsw_boot) = 1 ] && [ crossystem hwid = "$HWID_YOU_ASSIGNED" ] Cherry-pick: 5f30788 Change-Id: Id29b56748fafc6ad64cd336207ac7ef43befbbf5 Reviewed-on: http://gerrit.chromium.org/gerrit/1004 Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-08-29Implement cold rebootChe-Liang Chiou
The verified boot spec requires that firmware cold (not warm) reboots so that TPM gets reseted. BUG=chrome-os-partner:3574 TEST=manual 1. Run load_fw twice, and verify that SetupTPM failed in the second run ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... DEBUG: TPM: SetupTPM(r0, d0) ... DEBUG: TPM: SetupTPM() succeeded ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... DEBUG: TPM: SetupTPM(r0, d0) ... DEBUG: Unable to setup TPM and read stored versions. ------------------------------------------------------------ 2. Run load_fw twice and a reset in between, and results the same ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... CrOS> reset ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ------------------------------------------------------------ 3. Run load_fw twice and a "cros cold_reboot" in between, and verify that SetupTPM succeeds in both runs ------------------------------------------------------------ CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ... CrOS> cros cold_reboot ... CrOS> cros load_fw 0x0 0x01000000 0x00400000 0x10000000 ------------------------------------------------------------ Cherry-pick: bbb6ba7 Change-Id: Ie74bb214c80714d1814b4ae295c4780aa2bc7ddc Reviewed-on: http://gerrit.chromium.org/gerrit/756 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
2011-08-29Remove TPM functions and x86-specific CPU stateChe-Liang Chiou
The removed TPM functions are implemented in verified boot reference library (vboot_reference), and so this commit removes the implementation of these functions in u-boot. This commit also removes codes that are related to x86-specific CPU state (S3 resume). BUG=none TEST=CROSS_COMPILE=armv7a-cros-linux-gnueabi- ./MAKEALL chromeos Cherry-pick: 75707bc Change-Id: Id4a967b9dd16549bb26adbe27ce96caa713bfe30 Reviewed-on: http://gerrit.chromium.org/gerrit/515 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2011-08-24Refactor firmware storage interfaceChe-Liang Chiou
Note: The implementation of SPI interface is empty here and is sent out in cl/6696066 to reduce the size of this CL. The following test results are conducted with cl/6696066. 1. Verify that bootstub can boot to rewritable firmware 2. Verify that refactoring does not break load_fw ------------------------------------------------------------ (Read firmware image from SPI flash) CrOS> sf probe 0 SF: Detected W25Q16B with page size 256, total 2 MiB 2048 KiB W25Q16B at 0:0 is now current device CrOS> sf read 0x01000000 0 0x00400000 (Test load_fw) CrOS> cros load_fw 0 0x01000000 0x00400000 0x10000000 LoadFirmware returns: LOAD_FIRMWARE_SUCCESS: firmware_index: 0 ------------------------------------------------------------ 3. Verify that refactoring does not break load_k ------------------------------------------------------------ (Following from previous command) (Insert Chrome OS image into SDCard slot) CrOS> mmc init 1 EMMC 1 Probed Successfully mmc1 is available CrOS> cros bootdev set mmc 1 Set boot device to mmc 1 0 (Test load_k) CrOS> cros load_k 0 0x10000000 SF: Detected W25Q16B with page size 256, total 2 MiB boot_flags: 0x00000004 shared_data_blob: 0x10000000 kernel_buffer: 0x027012f0 success: good kernel found on device kernel_buffer: 0x0040c000 partition_number: 2 bootloader_address: 0x736000 bootloader_size: 0x1000 partition_guid: fa e2 d2 39 82 ab 4b ff 93 b7 25 5e 88 a4 18 54 bytes_per_lba: 512 ending_lba: 0x003ce022 ------------------------------------------------------------ Change-Id: I12d24f8df2535a1cd58e120552431b9314224f6e R=robotboy@chromium.org,waihong@chromium.org BUG=none TEST=see above Review URL: http://codereview.chromium.org/6676109
2011-08-24Refactor firmware and kernel loaders to improve code sharingChe-Liang Chiou
The bootstub should output like the following: ------------------------------------------------------------ U-Boot 2010.09-00059-ga8a8981 (Mar 16 2011 - 14:00:35) Board: Tegra2 chromeos/tegra2/seaboard/stub DRAM: 1 GiB Using default environment In: tegra-kbc Out: lcd Err: lcd Hit any key to stop autoboot: 0 DEBUG: LoadFirmware started... DEBUG: Checking key block signature... DEBUG: Firmware 0 is valid. DEBUG: Checking key block signature... DEBUG: Will boot firmware index 0 ------------------------------------------------------------ The cros load_fw command should output like the following: (assume you load firmware image at [0x01000000:0x011d0000] ------------------------------------------------------------ CrOS> cros load_fw 0 0x01000000 0x001d0000 0x10000000 DEBUG: LoadFirmware started... DEBUG: Checking key block signature... DEBUG: Firmware 0 is valid. DEBUG: Checking key block signature... DEBUG: Will boot firmware index 0 LoadFirmware returns: LOAD_FIRMWARE_SUCCESS: firmware_index: 0 ------------------------------------------------------------ Type following command in developer firmware: (Assume that you inserted a Chrome OS SD card image) ------------------------------------------------------------ CrOS> mmc init 1 EMMC 1 Probed Successfully mmc1 is available CrOS> cros bootdev set mmc 1 Set boot device to mmc 1 0 CrOS> cros load_k 4 0x10000000 boot_flags: 0x00000004 shared_data_blob: 0x10000000 success: good kernel found on device kernel_buffer: 0x0040c000 partition_number: 2 bootloader_address: 0x736000 bootloader_size: 0x1000 partition_guid: fa e2 d2 39 82 ab 4b ff 93 b7 25 5e 88 a4 18 54 bytes_per_lba: 512 ending_lba: 0x003ce022 ------------------------------------------------------------ R=waihong@chromium.org BUG=None TEST=MAKEALL successfully and run commands above Review URL: http://codereview.chromium.org/6688063 Change-Id: Ia4f44a9de1703c7cef0f6b52d8bc951ff1cb81ee
2011-08-24Rename caller_internal_t to firmware_storage_tChe-Liang Chiou
Renaming the caller_internal_t for better reflecting its purpose. BUG=chromium-os:1302 TEST=MAKEALL successfully Review URL: http://codereview.chromium.org/6594066 Change-Id: I0e28c5934fdbd198ab4fdb278a33d4707767b3c6
2011-08-24Fix copyright statementChe-Liang Chiou
BUG=None TEST=None Review URL: http://codereview.chromium.org/6602003 Change-Id: I6dd474c1d111499db8940a8aea43045b6e4e00a6
2011-08-24Implement GPIO accessor functionsChe-Liang Chiou
BUG=chromium-os:10496 TEST=build successfully and run "cros test_gpio" in u-boot Review URL: http://codereview.chromium.org/6546014 Change-Id: I30ad04bef6a6fc4ac0dc9ff2c17a1087b18d9909
2011-08-24Factor out verified boot required hardware interfaceChe-Liang Chiou
BUG=none TEST=emerge-tegra2_seaboard chromeos-u-boot-next Review URL: http://codereview.chromium.org/6543034 Change-Id: I88dfd38aedd81281415ecb8156181a6cc4d46495
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