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2020-03-05imx8mm-evk, imx8mm-val: take changed sd/mmc spl boot order into accountMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2020-01-15MLK-23241 imx8dx_mek: Add iMX8DX MEK board supportYe Li
iMX8DX MEK board has similar design with 8QXP MEK. The major changes are 1. DDR changed to 16bits 1GB DDR part 2. USB3.0 is removed and only support OTG on typec port. (No SW change needed) This patch adds new defconfigs and DTS file for this new board. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 5efb4275f6cfefb5dd342f2e498834b40b989883)
2019-12-31MLK-23179 board: imx8mn_evk: Update the ddr QoS setting on imx8mn ddr4 evkJacky Bai
The QoS setting is originally added in MLK-22001, but override when update the DDR script for DLL-ON only support, so add it back again. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-12-05MLK-23037 board: imx8mm_evk: update ddr4 timing for dll-on modeJacky Bai
Update the ddr4 timing file for 2400mts & 1066mts for dll-on mode only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit f7ed1fd1416f15764cca13993a054963996f6c50)
2019-12-05MLK-23027 imx8mm/imx8mn: Adjust MMC bus width in SPLYe Li
The SPL codes for both EVK and validation board set the MMC bus width to 1 bit for both emmc and SD ports. This causes slow image loading. Change to 8 bits for emmc and 4 bits for SD. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0859140a862ad1cc16f4e49247868595a6e62b38)
2019-12-05SSI-87: imx8: Configure SNVSFranck LENORMAND
Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> (cherry picked from commit 75aa7f2254f0883aa14568ac32702b1ca15367e4)
2019-11-01MLK-22881 board: imx8mn: Update the DDR4 timing script on imx8mn ddr4 evkJacky Bai
On i.MX8MN, we can only support DLL-ON mode only, so update the timing to support 2400mts & 1066mts setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-10-24MLK-22832 board: imx8mn_evk: Fix the retention hang on imx8mn lpddr4 evkJacky Bai
The '0x20060' register is used for phy memory reset, should not be put in the ddrphy config section, so remove it from the timing script, otherwise, ddr retention can NOT work. Additionally, the'0xd0000' register config in phy section is redundant, remove it too. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-16MLK-22762 imx8mn_ddr4_evk: Set VDD_SOC to 0.85v in suspend modeYe Li
According to datasheet, the VDD_SOC should be 0.85v in suspend mode. But current voltage is default 0.80v because we don't configure BD71837 BUCK1_VOLT_SUSP register. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-15MLK-22759-3 imx8mn: Add LPDDR4 EVK board supportYe Li
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and PCA9450B PMIC. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-15MLK-22759-1 imx8mn: Use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK boardYe Li
To align with other iMX8M platforms, use CONFIG_TARGET_IMX8MN_DDR4_EVK for DDR4 EVK board and will use CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-07-30MLK-22179-2 imx8mn_evk: Enable FSPI DQS loopback for high freqYe Li
There is an divider on imx8mn will always divide 2 to flexspi root clock. So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz. After changing the root clock setting to configure SCLK to 100Mhz, found the read data is not correct. Must enable the internal DQS pad loopback to fix the problem. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-12MA-15087-4 Support mmc loader for imx8mn_evkHaoran.Wang
Align using emmc loader when there is no Trusty OS for Android standard boot in SD/EMMC. Add hook for getting correct offset when load uboot. Change-Id: I5898cf196e734ffaca1a513918a049ce504b14e9 Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
2019-07-09MLK-22240 imx8m: Fix GPR setting issue for ENET TX CLK selectYe Li
Should use IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK not the IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT for clrsetbits_le32. This cause to clean other bits. Because the GPR1 is 0 by default, so this typo does not cause any issue but should be fixed. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-08MA-14981-1 Add evk_imx8mm 4GB DDR supportJi Luo
Add configs to support evk_imx8mm 4GB DDR board. The 4GB DDR will be split into two banks, one is 3GB (0x4000_0000~0xffff_0000) and another is 1GB(0x1_0000_0000~0x1_4000_0000). Test: build and boot with or without trusty. Change-Id: I02f6465fc5709b15fd76820edb846452d011dd56 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-06-25MLK-22105-3 imx8/imx8m: spl: Move bss clean up before arch_cpu_initYe Li
Since rng_init is used arch_cpu_init, we have to clean up BSS section before it. Also remove the unnecessary memset to global data, because board_init_f_init_reserve already memset it. If we memset it in board_init_f, the gd->malloc_base is reset to 0 and will cause early malloc problem when CONFIG_MALLOC_F_ADDR is not set. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-21MLK-22080 imx8mn_evk: add SPL and u-boot build for nominal modeYe Li
Add imx8mn_ddr4_evk_nom_defconfig to generate SPL and u-boot to force SOC to nominal mode. So the VDD_SOC will be 0.85V and ARM will be fixed to 0.85V with DVFS disabled in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Anson Huang <Anson.Huang@nxp.com>
2019-06-19MA-14989-1 Add 2GB ddr support for AIYJi Luo
Add support for AIY 2GB DDR size. Wrap support for 3GB DDR board with CONFIG_AIY_LPDDR4_3G because of the limited ocram size. Test: build and boot on 2GB AIY board. Change-Id: I04da60cc0d0b22c6c32ff705bcab4095068ba6ea Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-06-12MLK-22001 imx8mn_evk: tune DDR4 QoS to improve performanceJian Li
DDR efficiency improved to 78% while runing LCDIF,GPU,CPU Signed-off-by: Jian Li <jian.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2019-06-05MLK-21950-02 board: imx8mn_evk: update the ddr performance settingJacky Bai
Update the ddr performance setting on i.MX8MN DDR4 EVK board. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-05-30MA-14893-2 Add android build target for imx8mnJi Luo
Add configs to support evk_imx8mn android build. Test: build and boot on eMMC and sd. Change-Id: Id5c63b31e45357d791425976358635c18de928eb Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-05-29MLK-21889-11 imx8mn_evk: Add board codes and defconfig for iMX8M Nano EVKYe Li
Add board level codes, header file, and defconfig for iMX8M Nano EVK board. The board has similar design as iMX8MM EVK. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-05-21MLK-21745-02 board: imx8mm_val: change the ddr init to the common driverJacky Bai
change the ddr init to use the common driver init driver as we used on EVK board. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-05-21MA-14785-1 Limit display resolution to 720p for 1G ddr AIYJi Luo
Set the display resolution to 720p for 1G ddr AIY board to save some memory. Test: build and boot on AIY. Change-Id: I3ed56b371f849ce217f2ca58529b4d3b39e285c5 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-04-18MA-14629 fix build warnings for varialbe initialization and type castfaqiang.zhu
initialize potential uninitialized variable with the type of"char*" to be NULL in AVB. That "hashtree_error_mode" in code is manually specified with a known value, the cases listed cover all potential value of "hashtree_error_mode" explicitly do a type cast for memcpy parameters. Change-Id: Ie5d234422a273d6dab75585bd0d8eb81583707ca Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
2019-04-11MA-14511 AIY: Change the GPU reserved memory to 32MJi Luo
Reserve 32M memory for GPU on AIY 1G DDR board. Change-Id: I566a4a027982c8d4e41f280162f2f3cd67f1f5cd Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-04-11MA-14521 AIY: Explicitly set USB Switch (PTN5150A) to UFPMichael Brooks
* The default configuration (via resistor stuffing) is DFP (host). This means that on Type-C hosts fastboot won't work. * Set to UFP to ensure fastboot works properly. Change-Id: I2b63d95e08df70da43dee1f8f7bb59d1863943f4
2019-04-11MA-14520 AIY: Limit USB to High SpeedMichael Brooks
* There is an enumeration problem when using superspeed. * This doesn't fix it with all hubs, but can enable fastboot to work on some 3.0 hosts. Change-Id: If4a603126b945bd8f84c3d6e975e1185530eb193
2019-04-11MA-14519 Phanbell: Explicitly set buck voltages in SPLMichael Brooks
* Bucks 1-4 will be reconfigured via DVS in the kernel. * Buck 5 is explicitly set to 1.0V * Regulator lock/unlock is added, this ensures that in warm or cold reset the values will be set. Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77
2019-04-01MA-14494 Support DVT AIY 1G boardJi Luo
Add support for DVT AIY 1G board, distinguish the board type with the board id. TYPE: ID: Micron 1G 0x5 HYNIX 1G 0x3 Micron 3G 0x1 Test: Boot on AIY 1G/3G ddr board. Change-Id: I3c7b6ebe8bc5d4e59917fcc3947e9ebfefc940da Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-03-21MLK-21214 board: imx8mm_evk: Use the default QoS setting for imx8mm_evk ddr4Jacky Bai
previous setting can NOT meet the USB stream mode performance settting. So use the default QoS setting on the i.MX8MM DDR4. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-03-15MLK-21068 board: imx8mm_evk: update the lpddr4 timing configJacky Bai
Update the lpddr4 timing config to align with the ddr tool Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-02-25MLK-20987-2 imx8qm/qxp: spl: Clean the flexspi power up/down warningYe Li
When flexspi is assigned to M4 for XIP, its power up/down will fail. This is expected so don't need to give warning. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-02-25MLK-20987-1 imx8qm/qxp: spl: Fix SPL flexspi boot breakYe Li
The CONFIG_QSPI_BOOT has been removed from SPL flexspi build, because we have to change the u-boot ENV to SD/MMC, and this configuration will set relevant configurations. But we don't clean up CONFIG_QSPI_BOOT for SPL completely, SPL still has some places using it and cause problem to flexspi boot. Using CONFIG_SPL_SPI_SUPPORT to replace the CONFIG_QSPI_BOOT. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-02-26MA-14129 Update ddr training code for imx8mq_aiyJi Luo
Update the ddr training code to work with the atf 2.0. Test: Build and boot on imx8mq aiy 3G board. Change-Id: I8546c34cfa4aeeed819f7797f8362676e420b41f Signed-off-by: Ji Luo <ji.luo@nxp.com>
2019-02-25MLK-20980 imx8qm/qxp_mek: Set kernel fdt according to M4 bootYe Li
When M4 is booted by ROM, we have to enable RPMSG in kernel, so need to select the -rpmsg.dtb. If M4 is not enabled, use default kernel dtb. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-02-11MLK-20886-11: imx8qxp_mek: Remove GPIO1_1 for IO Expander resetYe Li
Since we have asked SCFW to do this job to avoid issues in partition reboot, remove relevant codes. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-02-10MLK-20902 imx8mm_evk: Change VDD_DRAM to 0.975vYe Li
According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC does not support 0.95v output. We change the voltage to 0.975v as the note in datasheet mentioned it is acceptable and supported. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
2019-01-24MLK-20796 imx8qm_mek: Remove base board resetYe Li
SCFW has taken to reset the base board by deasserting BB_PER_RST_B(SCU_GPIO0_01) on imx8QM MEK board, and has removed the SC_R_BOARD_R1 functionality. So We don't need to explicitly use SC_R_BOARD_R1, delete the codes from u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-24MLK-20794-2 imx8qxp_arm2: Add support for 17x17 validation boardsYe Li
There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010) for imx8x family 17x17 chips. These two boards have same design except the DDR. Since SCFW is resposible for DDR initialization, U-boot could use one build to cover two boards. The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and LPDDR4. Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig: one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL but with different FDTs. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-21MLK-20783 imx8mm: spl: Change VDD_SOC to typical value 0.85VYe Li
According to the latest datasheet, software is expected to program the VDD_SOC voltage to the typical value 0.85V prior to the first DRAM memory access. At default the VDD_SOC is 0.8V from PMIC BUCK1, so we have to change it to 0.85V in SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-21MLK-20781-4 mx7ulp_evk: Enable new mipi panel RM68200_WXGAYe Li
Enable the new mipi panel driver and add parameters to board codes. We enable the RM68200_WXGA as default panel, users can set "panel" environment variable to switch to different panel. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fancy Fang <chen.fang@nxp.com>
2019-01-08MLK-20559-8 imx8qm/qxp: Update MEK board codes to support UUUYe Li
Enable the SPL SDP driver and USB driver in MEK board codes and defconfigs. Because the USB driver needs larger malloc pool, increase the malloc size and disable simple malloc Signed-off-by: Ye Li <ye.li@nxp.com>
2019-01-08MLK-20559-7 tcpc: Bypass the vbus disable for SPLYe Li
The SPL won't use host mode, and the tcpc is default set as device mode. So we don't need to access tcpc in SPL. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-12-26MLK-20655-2 imx8qm/qxp: Fix wrong gpio resource used in SPLYe Li
Since the gpio non-dm driver maps to wrong GPIO register, the SPL also powers up wrong GPIO resources. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2018-12-19MLK-20583-2 imx: mx6sabreauto: Enable OCOTP CTRL clock in DCD and pluginBreno Lima
The HAB code can not set Field Return and SRK Revoke sticky bits in case OCOTP CTRL clock is gated out. In case we disable OCOTP CTRL clock in DCD and plugin those features may not operate as expected. Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock those features, users should use the CSF Unlock command to prevent those features from being locked. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-12-19MLK-20583-1 imx: mx6sabresd: Enable OCOTP CTRL clock in DCD and pluginBreno Lima
The HAB code can not set Field Return and SRK Revoke sticky bits in case OCOTP CTRL clock is gated out. In case we disable OCOTP CTRL clock in DCD and plugin those features may not operate as expected. Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock those features, users should use the CSF Unlock command to prevent those features from being locked. Signed-off-by: Breno Lima <breno.lima@nxp.com>
2018-12-18MLK-20493-6 imx8mq_evk/arm2: Set usb to be super speedLi Jun
Keep high speed for SPL, but for normal uboot, enable super speed. Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Tested-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
2018-12-12MLK-20542 imx8qm: xen: mek: add magic numberPeng Fan
Write magic number in board early init, and clear magic when booting Linux. This is to let XEN know the current EL1 code is U-Boot or Linux when reset/reboot. This is just a workaround because CM41 could not communicate with XEN now, even XEN knows that EL1 is reseting/rebooting. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Flynn xu <flynn.xu@nxp.com>
2018-12-11MLK-20528-2 imx8: Enable clocks LPCGYe Li
To support partition reboot, the u-boot has to enable clocks by LPCG. The LPCG will reset to default value only when the subsystem is totally power off and reset. However, the resources in one subsystem may belong to different partitions, so the partition reboot may not reboot the entire subsystem. Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and HW design. Thus, AP software has to ensure everything is reset by SW itself to support such above cases. Signed-off-by: Ye Li <ye.li@nxp.com>
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