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Add support for new target imx8mq_aiy.
Test: build and boot ok on imx8mq_aiy.
Change-Id: I7bb8b66e5235a7122073dcfb4cdc7f165036b9a6
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
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- temp fix for boot hangup with camera
This reverts commit a8109598e7dca72d415ad5d26ac5868b88da9dfc.
Bug: 115532706
Test: test boot up
Change-Id: I7bb1bc14eb81ae0965fc03abdf5cb65444720d13
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Add fastboot commands "fastboot oem at-get-vboot-unlock-challenge"
and "fastboot oem at-unlock-vboot" to support the authenticated
unlock feature for Android Things devices. Use software random
numbers generator to generate the 16 bytes random challenge, it
should be replaced with hardware encrypted random generator when
the TEE part is ready.
Test: Generate unlock challenge by:
./avbtool make_atx_unlock_credential
--output=atx_unlock_credential.bin
--intermediate_key_certificate=atx_pik_certificate.bin
--unlock_key_certificate=atx_puk_certificate.bin
--challenge=my_generated_challenge.bin
--unlock_key=testkey_atx_puk.pem
validated the unlock credential successfully on imx7d_pico
and AIY.
Change-Id: I4b8cee87c9e96924169479b65020a081136681f6
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Trusty image should be loaded to different address for AIY 1G/3G ddr
board which have different ddr size. Use board id to distinguish
different baseboard, load trusty image to 0x7e00_0000 for AIY 1G ddr
board and 0xfe00_0000 for AIY 3G ddr board.
Test: build and boot Trusty ok for AIY 1G/3G ddr board.
Change-Id: I62d8a19b13fe19f38075512a6faa4bbb36f74791
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Because sysdeps.h in trusty include stdint.h, so we need to define
USE_STDINT.
Test: Local build test and flash on imx7d. Verify provision som
key and product key succeed.
Bug: None
Change-Id: I08db7c10dd4453a87f15ff4432335fe4c41f9c5f
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for 1GB ram: cma=296M galcore.contiguousSize=8388608
for 3GB ram: cma=384M
Test: Boot successfully on AIY-1G & AIY-3G
Change-Id: If082d5b751b5a5e06efe301c0b8e49ec4ac3dfb7
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5262
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
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Set BUCK2 output for VDD_ARM to 0.85v
Set BUCK3 output for VDD_GPU off
Set BUCK4 output for VDD_VPU off
Change-Id: I26b47b72ae6b8e714d12345b20324490f0947f56
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5177
Reviewed-by: zhang bo <bo.zhang@nxp.com>
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The power domain driver is not ready when running board_early_init_f,
but we call it imx8qxp_gpmi_nand_initialize. so this cause u-boot reset
in early stage.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Han Xu <han.xu@nxp.com>
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Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Because u-boot USB gadget only can support one driver, so if we enable
ci_udc driver, the cdns3 gadget driver must be disabled. This cause build
error because we don't wrap the cdns gadget functions with its configuration.
Fix the issue by adding CONFIG_USB_CDNS3_GADGET before cdns3 gadget function.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Because the iMX8MQ DDR4 ARM2 has 4GB DDR. To fit new MMU settings, we split
it to two banks. The first bank has 3GB DDR, reach to 4GB memory map.
The second bank has 1GB DDR, is beyond 4GB memory map.
Notice: there is no OPTEE for ARM2 board. The trust zone setting in OPTEE
for iMX8MQ EVK is not match with DDR size on ARM2 board. So ARM2 Only can
work without OPTEE.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash
on ECSPI1 port. Update the codes and configurations to enable the
ECSPI1 to access SPI NOR in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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The iMX7ULP B0 chip has added more pins for muxing USB ID. The A3 board
follows it to exploit PTC13 for USB ID, so we don't need to use GPIO
any longer. The USB driver can recognize the USB mode from USB PHY.
After this change, old boards with design using GPIO for USB mode won't
be supported.
Signed-off-by: Ye Li <ye.li@nxp.com>
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enable CE_1 IOMUX setting for NAND on i.MX8MM EVK
Signed-off-by: Han Xu <han.xu@nxp.com>
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Update the RFSHCTL3 config for DDR4.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.
There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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Add support for FIT image loading of ATF and uboot proper for iMX8QXP mek.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Add support for FIT image loading of ATF and uboot proper for iMX8QM mek.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Update the DDR4 MR value on i.MX8MM DDR4 EVK board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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The codes in imx8mq ARM2 SPL still return back to ROM when booting from
usb serial download. This is old way to support mfgtool not uuu.
Update the codes to support uuu when SPL SDP is enabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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For LPDDR4 and DDR4, we use the same dram_timing struct
to config parameters. rename the 'lpddr4_timing' to
'dram_timing' for common use.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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We enable the pull-up resistor for i2c pad by setting the PAD_CTL_PUE.
But this requires to enable pull resistors first by setting PAD_CTL_PE on iMX8MM,
otherwise the pull-up won't work.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Allow iMX8QM mek SPL to boot from QSPI.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add spl implementation for iMX8QM MEK board.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add implementation for ARM2 LPDDR4 board
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Since we set the fdt_file value when running on iMX6ULZ. This
cause the saved fdt_file change be overwritten. So users can't
set to their own fdt_file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Since the mx6ulz don't have FEC, it needs to use USB2NET dongle
to connect network. We decouple the CONFIG_FEC_MXC with CONFIG_CMD_NET.
For 6ull, all defconfigs need to enable the CONFIG_FEC_MXC explicitly.
Another change is adding ${usb_net_cmd} environment for usb start command
in netboot scripts on 6ulz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Allow iMX8QXP SPL to boot from QSPI.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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Add SPL and u-boot support to load images from RAWNAND device when booting
from RAWNAND. The NAND SPL loads the FIT image from nandfit mtdpart at 64MB
offset of NAND. Users need uuu to burn the FIT image, kernel, DTB and rootfs
to all fixed mtdparts.
Since NAND SPL needs large BSS and MALLOC size, this patch also moves the MALLOC
pool to DDR, and enable MALLOC_F pool on OCRAM for all malloc before DDR initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add i.MX6ULZ support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Separate tcpc related operations with config CONFIG_USB_TCPC
so we can enable/disable this feature separately.
Test: Boot ok on both imx8qm/8qxp_mek.
Change-Id: I46ef775e8deb4443944c0e969a4ced67c11ac48c
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Add DDR4 init codes, u-boot dtb and defconfig to support DDR4 EVK.
The DDR4 EVK removed eMMC and Flexspi, but use NAND instead. Current
codes support to boot from SD and enable NAND access in regular u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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To support the uuu, pack the common qspi header with u-boot binary for
i.MX6/7 qspi u-boot.
Signed-off-by: Han Xu <han.xu@nxp.com>
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enhance memory controller performance and QoS setting
Signed-off-by: Tom.zheng <haidong.zheng@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit ae7b37d3ed72bad542c8e77db4bbc0325180d6d2)
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This commit is basically cherry-picked from:
commit ced8dc6ce85f2227a29a52d55836b73223e71e73
Author: Ye Li <ye.li@nxp.com>
Date: Mon Aug 20 23:35:20 2018 -0700
MLK-19263-2 imx8mq_evk: Adjust SPL malloc pool and stack address
Currently the SRAM is allocated to malloc pool due to large malloc
needed by USB SDP. The stack is moved to OCRAM. This causes a
problem when enabling HAB. The HAB authentication needs large
memory on stack, so after ATF image loaded, the stack overwrites
the ATF image in OCRAM and causes authentication failed.
This patch moves the malloc pool to DDR and set back stack to
SRAM. So SDP still can run with enough memory on DDR. And the
stack overwrite issue can be fixed by enough memory 24KB left on
SRAM.
This change also need to use a early malloc pool by defining the
CONFIG_MALLOC_F_ADDR. And in SPL codes, we have to adjust DDR init
before board_init_r.
Signed-off-by: Ye Li <ye.li@nxp.com>
Change-Id: I37e0d196296b6b25662dda3dbbbc265bdf6d983f
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Sync configs with BSP team to enable uuu for imx8m AIY board,
create new file imx8mq_phanbell_androidthings_uuu_defconfig
for uuu image build.
Test: uuu works on imx8m AIY board.
Change-Id: Ied7cbb6d45d084837495cec5eeb5b4947a0630c4
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Currently the SRAM is allocated to malloc pool due to large malloc needed
by USB SDP. The stack is moved to OCRAM. This causes a problem when enabling
HAB. The HAB authentication needs large memory on stack, so after ATF image loaded,
the stack overwrites the ATF image in OCRAM and causes authentication failed.
This patch moves the malloc pool to DDR and set back stack to SRAM. So SDP still
can run with enough memory on DDR. And the stack overwrite issue can be fixed by
enough memory 24KB left on SRAM.
This change also need to use a early malloc pool by defining the CONFIG_MALLOC_F_ADDR.
And in SPL codes, we have to adjust DDR init before board_init_r.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
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The hdmi rx firmware is appended to the end of u-boot binary,
load it in u-boot, this will increase the size of u-boot binary
by 128k.
Test: hdmi rx firmware loaded successfully on imx8qm_mek.
Change-Id: Ib8e8ecd70a35b56ba4498c21d8c4716f6ad6405a
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Change VDD_DRAM to 0.9V
Change-Id: Ia2d0672b2f31f18add6626ac2e23e66b8c421a75
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5139
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Change the VDD_3V3 and VDD_1V8 to lower one to save power.
Change-Id: I61f1f4ed8c6e036173d9adc5358db01bd9c835a2
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5144
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Decrease the phanbell DDR(1G + 3G) frequency to 1600
MTS, this may save some power.
Test: Boot ok on both 1G and 3G DDR board, the dram_core_clk
decrease from 800000000 to 400000000.
Change-Id: I73b78865e7691001a868061826f0211cb9927cee
Signed-off-by: Luo Ji <ji.luo@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5100
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Add 1G DDR support, distinguish different boards by the
Board ID, They are:
SAI5_MCLK: Board_id[6]
SAI5_RXFS: Board_id[5]
SAI5_RXC: Board_id[4]
SAI5_RXD3: Board_id[3]
SAI5_RXD2: Board_id[2]
SAI5_RXD1: Board_id[1]
SAI5_RXD0: Board_id[0]
Current Board ID for imx8m boards are:
AIY Micron 1G: 0x5c
AIY Hynix 1G: 0x56
AIY Mirconb 3G: 0x40
Wibo 3G: 0x00
imx8m_ref 3G: 0x00
Test: Boot ok on all imx8m boards.
Change-Id: I3d65931483f369c545632b660f04fc9da120547d
Signed-off-by: Luo Ji <ji.luo@nxp.com>
Reviewed-on: http://androidsource.ap.freescale.net/project/5093
Reviewed-by: guoyin.chen <guoyin.chen@nxp.com>
Reviewed-by: Wang Haoran <elven.wang@nxp.com>
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Fix build warnings in u-boot.
Change-Id: I1944657d2d89a03c0d2303a22a09538dfaa5fd2c
Signed-off-by: Luo Ji <ji.luo@nxp.com>
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Since the u-boot gadget class drivers don't support super speed, if
we set DWC3 gadget driver to super speed, the device mode will meet problem
when using USB3.0 cable. So force the DWC3 gadget driver to high speed
for both SPL and regular u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable TZASC on i.MX 8mm.
There is a need on 8MM to enable
the BYPASS ID SWAP bit (GPR10 bit 1) in order
for GPU not to generated AXI bus errors.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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