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2009-10-07* Following Bugs fixed(identified in Pre-alpha release). 1. DDR hang at 400 ↵Poonam Aggrwal
(Bug Id 3536) 2. Environment (Bug Ids 3577, 3578) * SYSCLK changes for P2020RDB RevC Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07NAND boot changes for P2020RDB RevB. Mainly related to DDR size, DDR ↵Poonam Aggrwal
configuration and SYSCLK values. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-RevB-DDR-changesPoonam Aggrwal
P2020RDB RevB changes mainly for DDR settings Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-DDR-size-config-Board-Rev-and-SOCPoonam Aggrwal
DDR size configurable according to Board Rev and SOC. If GPIO11 = 0... REV A board (512MB P2020 and 256MB P1020) If GPIO11 = 1... REV B board (1GB P2020 and 256MB P1020) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07NAND boot support for P1 P2 RDB PlatformsPoonam Aggrwal
Switch options for NAND boot are SW[1:4]='0101" To Boot from NAND 1. tftp 1000000 u-boot-nand.bin 2. nand erase 0 80000 3. nand write 1000000 0 80000 4. Change the Switch settings to boot from NAND. 5. reset the board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-SYSCLK-detected-from-GPIO10Poonam Aggrwal
SYSCLK getting detected from GPIO10 If GPIO10 = 0... SYSCLK = 66Mhz If GPIO10 = 1... SYSCLK = 50Mhz Board REV getting detected from GPIO11 If GPIO11 = 0... REV A board If GPIO11 = 1... REV B board. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-SDCARD-boot-supportDipen Dudhat
SDCARD boot support for P2020RDB Make a special uboot used for booting from SDcard for P2020RDB platform. This patch uses sdboot support for 8536DS posted by Mingkai Hu. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-SD-and-SPI-4-bit-data-modeDipen Dudhat
SD and SPI 4-bit data transfer mode selected Make both[SD and SPI] work at the same time. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-Boot-from-SDcard-MPC8536DS-v2Jason Jin
Make a special uboot used for booting from SDcard or SPI flash This Patch is borrowed from MPC8536DS SD Card Boot. This patch is used to generate a special version u-boot, together with the data structure on the SDcard/SPI flash, can be used to booting from SDcard/SPI flash on 8536DS board. The boot ROM in CPU and the data structure on SD card will initialize the DDR, set a large tlb0 for DDR and CCSR, set law0 for DDR. The special version uboot avoid initializing the DDR. Try to reseve the law0 for DDR by adding a CONFIG_SYS_RESERVED_LAW0 macro for the "dynamic law allocation" code. But keep the original tlb initialize code for DDR, disabled the large tlb0 which was set in the boot ROM. This patch is intend for those who are interested in the function of booting from SD card on 8536DS board and not for opensource. An utility is needed to write the data structure and the special version u-boot onto the SD card which has filesystem on it or onto the SPI flash. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-eSPI-controller-support-MPC8536DSMingkai Hu
Add eSPI controller support under the SPI framework. This Patch borrowed from MPC8536DS SPI Support. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-10-07u-boot-2009.03-p2020rdb-Support-for-P1-P2-RDB-platforms-v2Poonam Aggrwal
Support for P20x0 RDB Platforms. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2009-03-17ColdFire: Fix M5329EVB and M5373EVB nand issueTsiChung Liew
The Nand flash was unable to read and write properly due to Nand Chip Select (nCE) setup was in reverse order. Also, increase the Nand time out value to 60. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2009-03-09fsl: Remove unnecessary debug printfsAndy Fleming
These were left in accidentally, and are not really useful unless the code is as broken as it was when it was being developed. Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-03-09Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
Conflicts: lib_ppc/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-03-05mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signalAnton Vorontsov
The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-24Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2009-02-23mpc83xx: MPC837XERDB: Add PCIe supportAnton Vorontsov
On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe slots. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-23mpc8641hpcn: Indicate 36-bit addr map in boot messagesBecky Bruce
If 36-bit addressing is enabled, print a message on the console when we boot. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-1683xx: Add eSDHC support on 8379 EMDS boardAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-1686xx: Reset updatePeter Tyser
Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-1685xx: print boot header info to distinquish 36-bit addr map on MPC8572 DSKumar Gala
Added some info that is printed out when we boot to distiquish if we built MPC8572DS_config vs MPC8572DS_36BIT_config since they have different address maps. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16Fixup SGMII PHY ids in the device treeAndy Fleming
The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card. The 8572, 8536, and 8544 DS boards were modified to call this function. Code idea taken from Liu Yu <yu.liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-1685xx: Fix bug in device tree setup in 36-bit physical confgKumar Gala
In the 36-bit physical config for MPC8572DS when need the start address of memory and it size to be kept in phys_*_t instead of a ulong since we support >4G of memory in the config and ulong cant represent that. Otherwise we end up seeing the memory node in the device tree reporting back we have memory starting @ 0 and of size 0. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-1685xx: Fix address map for 36-bit config of MPC8572DSKumar Gala
When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-10mpc8641hpcn: Clean up PCI mapping conceptsBecky Bruce
Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-10mpc8641hpcn: Set up outbound pci windows before inboundBecky Bruce
Because the inbound pci windows are mapped generously, set up the more specific outbound windows first. This way, when we search the pci regions for something, we will hit on the more specific region. This can actually be a problem on systems with large amounts of RAM. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-07pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-28mpc8536ds.c: include sata.h to for needed function prototypesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-28Command usage cleanupPeter Tyser
Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28Standardize command usage messages with cmd_usage()Peter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28Clean up diufb command definitionsPeter Tyser
The diufb command usage formatting is non-standard. It was made standard in preparation for larger command usage updates. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-27SATA: do not auto-initialize during bootMike Frysinger
Rather than have the board code initialize SATA automatically during boot, make the user manually run "sata init". This brings the SATA subsystem in line with common U-Boot policy. Rather than having a dedicated weak function "is_sata_supported", people can override sata_initialize() to do their weird board stuff. Then they can call the actual __sata_initialize(). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-24Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2009-01-2385xx: enable the auto self refresh for wake up ARPDave Liu
The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23fsl-ddr: use the 1T timing as default configurationDave Liu
For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala
Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala
Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boardsKumar Gala
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-2385xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate FLASH BASE virtual from physical addressKumar Gala
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate PIXIS virtual from physical addressKumar Gala
Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-21mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov
MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21mpc83xx: Add PCI-E support for MPC8315ERDB boardsAnton Vorontsov
MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-21MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent modeIra Snyder
When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do not enable them. See the MPC8349EA Reference Manual, Section 4.4.2 "Clocking in PCI Agent Mode". Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-14Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2009-01-13Some changes of TLB entry setting for MPC8572DSHaiying Wang
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13Change PCIE1&2 deciide logic on MPC8544DS board more readableRoy Zang
The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bitRoy Zang
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
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