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From IC spec:
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1.Considering pfuze tolerance and IR drop and board ripple, need rise from
1.375V to 1.425V. Only for Sabresd.
2.workaround pfuze1.0 ER1, set all buck regulator except SW1C to PWM mode.
now for mx6sl_arm2 and mx6_sabresd.
Signed-off-by: Robin Gong <B38343@freescale.com>
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enable SD3.0 support on SD1 and SD2 on mx6sl arm2 cpu board.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Move the secure boot related implementation code from mx6q_arm2.c to
mx6/generic.c. In this way the HAB feature can be shared by all MX6
platforms
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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1.enable I2C and I2C bus recovery support on mx6sl_arm2
2.enable LDO bypass on u-boot, by configuring 'CONFIG_MX6_INTER_LDO_BYPASS'
Signed-off-by: Robin Gong <B38343@freescale.com>
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- add android build config for mx6sl_arm2 board.
- add gpio support for mx6sl
- add boot image support
- add android recovery support
- add fastboot support, but fastboot cannot transfer file.
Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
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Since FEC_RX_ER is not connected with PHY(LAN8720A), we need
either configure FEC_RX_ER PAD to other mode than FEC_RX_ER,
or configure FEC_RX_ER PAD to FEC_RX_ER but need pull it down,
otherwise, FEC MAC will report CRC error always. We configure
FEC_RX_ER PAD to GPIO mode here and remove the SW hack which
ignore the CRC error in fec driver
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch is to add the initial support for i.mx6sl ARM2 board, the patch does:
- implemention of LPDDR2 init script
- Plug-in/DCD mode support to do DDR initialization
- Debug UART(UART1) support
- SPI-NOR(M25P32, 4MB) flash support
- FEC support, PHY(LAN8720A, RMII mode)
- SD/MMC card support, SD1/SD2/SD3
Signed-off-by: Danny Nold <dannynold@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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