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1. enable fastboot feature on mx6q-arm2 board
2. enlarge fastboot buffer to 320MB
3. correct some usb descriptors
Signed-off-by: LiGang <b41990@freescale.com>
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The original secure boot implementation make a consumption that
u-boot.bin will not exceed 0x2F000. With this consumption, the hab data
is hard coded in linker script file to relative address 0x2F000 without
causing any problem.
But when this consumption don't hold, the hard coded way will cause
memory region overlap and break build. So we need to change to a dynamic
way of allocating hab_data. The new implementation put hab data at the
next 0x1000 alignment after u-boot data and text section, instead of
hard coded to 0x2F000.
Similar changes is made to uImage authentication implementation.
Changes in U-Boot includes:
- in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000
- change authenticate_image implementation, originally the uImage
parameters are hard coded, now they are retrived from the
"load_addr" and the image_hdr
The new secure image layout:
U-Boot
+-------------------+ DDR_START
| |
| U-Boot Image |
| |
+-------------------+ DDR_START + UBOOT_SIZE
| PADDING |
+-------------------+ align to 0x1000
| CSF Data | -
+-------------------+ +-- CSF + Pad, Size : 0x2000
| PADDING | -
+-------------------+
uImage
+-------------------+ DDR_START
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| uImage |
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+-------------------+ DDR_START + UIMAGE_SIZE
| PADDING |
+-------------------+ align to 0x1000
| IVT | ---- Size : 0x20
+-------------------+
| CSF Data | -
+-------------------+ +-- CSF + Pad, Size : 0x2000
| PADDING | -
+-------------------+
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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The silicon revision is not printed correctly, on ARM2
and sabrelite board, the log is just as the following:
CPU: Freescale i.MX6 family TO0.0 at 792 MHz
We need print the silicon revision correctly as:
CPU: Freescale i.MX6 family TO1.2 at 792 MHz
with i.mx6q TO1.2 chip
Signed-off-by: Jason Liu <r64343@freescale.com>
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This commit fix the linker error when enable more function(like CONFIG_NAND,
CONFIG_SPASHSCREEN,etc) in uboot ARM2 board, and a possable linker error for
other MX6 boards:
/home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/
bin/arm-eabi-ld: section .bss [27831000 -> 278666e7] overlaps section
.rodata [2782387c -> 278609eb]
/home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/
bin/arm-eabi-ld: section .rodata.str1.1 [278609ec -> 27867803] overlaps
section .bss [27831000 -> 278666e7]
One issue here is:
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script. Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.
Another issue is:
The secure boot feature require __hab_data section in uboot linker script,
but it's have a hard coding magic number, but if we enable more code, cause
.text section bigger, it will cross the line, so it report the
first linker error.
This commit disable SECURE_BOOT feature by default for android,
and comments if user want to use this feature, it needs change the
.lds by there configure.
Also, enlarge the magic number that this feature needs to cover
if more code is build in.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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With the secure boot patch. MX6 NAND Boot is not functional. The root
cause is that, the original secure boot patch fills "0xFF' to spacing
regions, due to a issue in ROM code, read pages of all "0xff" will be
treated as a critical error. Thus prevent the U-Boot from booting
normally.
The fix adjust image copy size in IVT so that when secure boot is not
enabled, no unuseful data is copied by ROM code. Also the secure boot
option is default disabled. The end user won't enable it unless they
know what they are doing.
These prevent the ROM code from copied pages of "0xff" data, and fix the
issue.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Move the secure boot related implementation code from mx6q_arm2.c to
mx6/generic.c. In this way the HAB feature can be shared by all MX6
platforms
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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For MX6DL LPDDR2 board, in order to use both the 2 channels of the memory, the
"PL301_FAST2" must be set to 0x1. However this bit is not accessible using
DCD. Plugin mode must be utilized for this purpose.
The patch can be verified this way:
Enter U-boot console
> mw.l 0x80000000 0xC0 10
> mw.l 0x10000000 0xC1 10
> md.l 0x10000000 10
> md.l 0x80000000 10
Before the patch, 0x10000000 and 0x80000000 in fact point to the
same memory location. So the last 2 dump will show memory content of
both 0x000000C1
After the patch, 0x80000000 ponit to channel 0, 0x10000000 point to
channel 1. the last 2 dump will show memory content of 0x000000C0
and 0x000000C1 respectively
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Move IPU QoS and VDOA/IPU/VPU AXI Cache config
to linux kernel in order to reduce code duplicate
Signed-off-by: Wayne Zou <b36644@freescale.com>
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We can use weak ODT setting, it will save about 50% DDR
power in runtime. Now we use 0x00007
MMDC0_MPODTCTRL MMDC1_MPODTCTRL, (Ohm)
Setting DDR_ODT imx_ODT Max_overclocking
0x22227 120 060 615MHz
0x11117 120 120 604MHz
0x00007 120 000 576MHz
0x00000 000 000 556MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
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- EPDC Splash support for MX6DL/S Sabre SD
- EPDC Splash support for MX6DL/S ARM2
- Currently, splash screen consists of a simple black border
around a white screen. Done this way to save in memory footprint.
Signed-off-by: Danny Nold <dannynold@freescale.com>
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Before running authentication on uImage in DDR, u-boot first check if
SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in
secure configuration, the authentication continues; if not, the chip
in not in secure configuration, just bypass the authentication
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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The first stage of High Assurance Boot (HAB) is the authentication of
U-boot. A CST tool is used to generate the CSF data, which include
public key, certificate and instruction of authentication process. Then
it is attached to the original u-boot.bin
The IVT should be modified to contain a pointer to the CSF data. The original
u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first
extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with
the CSF data. The combined image is again extend to a fixed length (0x31000),
which is used as the IVT size parameter.
The new memory layout is as the following.
U-Boot Image
+-------------+
| Blank |
|-------------| 0x400
| IVT |-----------------------+
|-------------| |
| | |
| | |
| | |
|Remaining UB | | CSF pointer
| | |
| | |
| | |
|-------------| |
| | |
| Fill Data | |
| | |
|-------------| 0x2F000 <-------------+
| |
| CSF Data |
| |
|-------------|
| |
| Fill Data |
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+-------------+ 0x31000
HAB APIs are ROM implemented, the entry table is located in a fixed
location in the ROM. We export them so that during the HAB we can
have some information about the secure boot process. For convinience
some wrapper API is implemented based on the HAB APIs.
- get_hab_status : used to dump information of authentication result
- authenticate_image : used by u-boot to authenticate uImage
For security hardware to function, CAAM related clock (CG0[4~6]) must
be open. They are default closed in the original U-boot.
"hab_caam_clock_enable" and "hab_caam_clock_disable" are created to
open and close these clock gates.
The generation of CSF data is not in the scope of this patch. CST tool
will be used for this purpose. The procedure will be introduced in
another document.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Apply script "Mx6DL_init_LPDDR2_400MHz_Micron_1.1.inc" in IVT, make U-boot
work for the LPDDR2 Board. The Make target name for the new board is
"MX6DL_ARM2_LPDDR2_CONFIG"
The script is provided by Chen Wei - B26879 for a quick bring up, which don't
have a corresponding compass link. It is uploaded to CR ticket page for
reference.
Originally for MX6DL DDR3 board, "CONFIG_MX6DL" is defined. It is used by
"board/freescale/mx6q_arm2/flash_header.S" to select the correct IVT. Since
MX6DL LPDDR2 board also define this macro, for distiguish purpose, another
2 macros "CONFIG_MX6DL_DDR3", "CONFIG_MX6DL_LDPPR2" are defined
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Add CONFIG_MXC_FEC macro to fec init code.
Add CONFIG_VIDEO_MX5 to ipu init code.
Change temperature function as static.
For in iram boot, FEC configs is not needed, those FEC init code will
cause build errors.
These changes can reduce image size.
Signed-off-by: Terry Lv <r65388@freescale.com>
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The 32bit DDR script got from the following link:
http://compass.freescale.net/livelink/livelink/225194568/
MX6DL_init_DDR3_400MHZ_32bit_1.0.inc.txt?func=doc.Fetch&nodeid=225194568
The DDR hw connection on the ARM2 board is 64bit wire, but we can make it use
as 32bit, the side effect is that DDR access size will reduce to the half
Signed-off-by: Jason Liu <r64343@freescale.com>
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The script we get from the following link:
http://compass.freescale.net/livelink/livelink/225193471/MX6DL_init_
DDR3_400MHz_64bit_1.1.inc.txt?func=doc.Fetch&nodeid=225193471
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch add the initial support for i.mx6dl ARM2 board
-SD/MMC basic
-DDR 400Mhz,
-FEC,basic
Due to i.mx6dl shares the same board with i.mx6q on ARM2,
the most common code should be the same as the i.mx6q ARM2
So, no need to create one seperate board file for i.mx6dl.
But We can't simply resue anything from the board file since
the i.mx6dl iomux is changed and thus we have to deal with the
difference between i.mx6q and i.mx6dl for the pad setting part.
Signed-off-by: Jason Liu <r64343@freescale.com>
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integrate DDR script http://compass.freescale.net/livelink/
livelink/225147268/rigel_temp.inc.txt?func=doc.Fetch
&nodeid=225147268
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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Disable the uboot workaround. It will crash the MFGTOOL.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code
Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.
There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily
The MMU Change can be concluded as the following
- Cacheable and Uncacheable SDRAM allocation changes to
Phys Virtual Size Property
---------- ---------- -------- ----------
0x10000000 0x10000000 256M cacheable
0x80000000 0x20000000 16M uncacheable
0x81000000 0x21000000 240M cacheable
- TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
of SDRAM. This address makes sure that the text section of U-boot have the
same Physical and Virtural address, thus the PC don't need to change when
MMU is enabled. Also the text section is all allocated in cacheable memory,
which may increase excecution performance.
- Since this SDRAM allocation avoid overlap in physical memory between
cacheable and uncacheable memory, the implementation of __ioremap can be
ignored
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Ungate the clocks to SD1 and SD2 ports (on baseboard of ARM2 system)
so that the above cmds do not hang waiting for cmd to complete or
timeout.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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- Add plugin DRAM init script in flash_header.S file.
- Define CONFIG_FLASH_PLUG_IN in mx6q_sabreauto.h to switch plugin mode.
- DDR support 528MHz and 480MHz in plugin mode.
Switch DDR clock to 480M according to define CONFIG_IPG_40M_FR_PLL3.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Move the code to read the mac address from the fuse to SoC file
and out of the board file
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add iomux and clock setting in Uboot code to support NAND, due to
the conflict between NAND and SD, NAND function is not enabled in
default configuration.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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Fix the code to read the MAC address correctly from the fuses
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add spi-nor support for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Sabreauto is an inaccurate name for the Armadillo2 board that
this code is actually meant for. So, replaced "sabreauto" in folder names,
file names, configs, and code with "arm2". Created a new machine id for
ARM2 board.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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