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Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the
driver reset the phy via dts description adding a reset duration of 10 ms
following atheros 8031's datasheet recommendation.
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
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A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Move env_set() over to the new header file.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
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Converted to use fsl_esdhc_imx for i.MX platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
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Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.
The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC: PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE: Configureing TZASC380
NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE: BL31: Built : 09:28:54, Nov 8 2018
lpddr4 swffc start
NOTICE: sip svc init
U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM: 3 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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