| Age | Commit message (Collapse) | Author |
|---|
|
Should use IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK not the
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT for clrsetbits_le32. This cause
to clean other bits.
Because the GPR1 is 0 by default, so this typo does not cause any issue
but should be fixed.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Since rng_init is used arch_cpu_init, we have to clean up BSS section
before it.
Also remove the unnecessary memset to global data, because
board_init_f_init_reserve already memset it. If we memset it in board_init_f,
the gd->malloc_base is reset to 0 and will cause early malloc problem
when CONFIG_MALLOC_F_ADDR is not set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Keep high speed for SPL, but for normal uboot, enable super speed.
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Tested-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
|
|
Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Because the iMX8MQ DDR4 ARM2 has 4GB DDR. To fit new MMU settings, we split
it to two banks. The first bank has 3GB DDR, reach to 4GB memory map.
The second bank has 1GB DDR, is beyond 4GB memory map.
Notice: there is no OPTEE for ARM2 board. The trust zone setting in OPTEE
for iMX8MQ EVK is not match with DDR size on ARM2 board. So ARM2 Only can
work without OPTEE.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
The codes in imx8mq ARM2 SPL still return back to ROM when booting from
usb serial download. This is old way to support mfgtool not uuu.
Update the codes to support uuu when SPL SDP is enabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Since the u-boot gadget class drivers don't support super speed, if
we set DWC3 gadget driver to super speed, the device mode will meet problem
when using USB3.0 cable. So force the DWC3 gadget driver to high speed
for both SPL and regular u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
When using SPL NAND boot, the required malloc memory is larger than SD/eMMC boot.
Since we have used out OCRAM (for ATF) and OCRAM_S, there is no enough memory could be
allocated.
The solution is moving the malloc memory pool to DDR. The malloc pool is initialized in
board_init_r, so we moved the VDD_DRAM adjustment and DDR init to board_init_f. Then the DDR
can setup before memory pool initialization. Because the i2c and PMIC driver needs to malloc
data, this change has to enable malloc_f pool by setting CONFIG_MALLOC_F_ADDR to previous
malloc address on OCRAM_S.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit ab1895fb5e38d216ff86de292a44776099d159ab)
|
|
Add board codes, configurations, DTS and DDR initialization codes for the
DDR3L and DDR4 ARM2 boards.
Supported modules
- DDR3L ARM2: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
- DDR4 ARM2: Two RANK DDR4, SD, NAND, RGMII ENET, UART.
NAND read/write/erase is ok in u-boot, NAND SPL boot will be tested later
when tool is ready.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
|
