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Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.
Signed-off-by: York Sun <yorksun@freescale.com>
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Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram
setting. SPD based parameters and fixed parameters can be toggled by hwconfig.
To use fixed parameters,
hwconfig=fsl_ddr:sdram=fixed
To use SPD parameters,
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The board specific parameters associated with quad rank dimms where
missing. This fixes it so the board will function if quad rank dimms
are placed in it.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add support for the P4080DS board, with the following features:
* 36-bit only
* Boots from NOR flash
* FMAN drivers NOT supported
* SPD DDR initialization
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Ashish Kalra <Ashish.Kalra@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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