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2020-04-27xilinx: Introduce board_late_init_xilinx()Michal Simek
This function should keep common shared late configurations for Xilinx SoCs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31arm: zynq: Add support for Bitmain Antminer S9 control boardEzequiel Garcia
This is control board on Bitmain Antminer S9. There are 3 board variables with 256MB, 512MB and 1024MB DDR. DDR memory is automatically detected with using get_with using get_ram_size(). Bitmain is using 16MB space for FPGA which is handled via reserved-memory. Also U-Boot is allocating 16B for storing bootcounts. Watchdog is started but never service in U-Boot. SPL MMC is working. SPL NAND is not working because it is not supported as of now. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>