| Age | Commit message (Collapse) | Author |
|---|
|
RC Release 09.02.00.010
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Add combined binaries for all Aquila AM69 variants.
These binaries can be used to flash the U-Boot via single
binary instead of few as it is done at the moment.
Upstream-Status: Pending
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
|
|
Add combined binaries for all Verdin AM62 variants.
These binaries can be used to flash the U-Boot via single
binary instead of few as it is done at the moment.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240605091057.48225-1-andrejs.cainikovs@gmail.com/]
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
|
|
Configure DDRSS using "J784S4 (Jacinto7) DDRSS Register
Configuration Tool (version 0.11.0)" targeting
"Micron MT53E2G32D4DE-046 AIT:C" memories.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
Set wkup_gpio0 status to enable and let it be available in U-Boot.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
Manually, since SysConfig tool do not have the relevant option,
set PHY_LP4_WDQS_OE_EXTEND to 1.
Since WDQS control mode is required on our modules LPDDR4,
this enables WDQS control mode 1.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240515080058.1530985-1-ghidoliemanuele@gmail.com/]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
Update the autogenerated LPDDR4 configuration using the latest available
SysConfig tool.
This changes are cosmetic and are made to track the last used tool version.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240515080058.1530985-1-ghidoliemanuele@gmail.com/]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
Use mac address for cpsw_port1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
|
|
Allow other boards to reuse the binman definition by using macros for
the board names
Signed-off-by: Nishanth Menon <nm@ti.com>
|
|
This adds initial support for the Toradex Aquila AM69 module.
Upstream-Status: Pending
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
msmc and ddrss probes do not depends on specific target boards but on
K3_J721E_DDRSS configuration.
So enable probe using this configuration.
Upstream-Status: Inappropriate
Upstream already probes these drivers using K3_J721E_DDRSS configuration.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
The memory node is already defined in k3-am69-sk.dts, remove the
duplicate node from k3-am69-r5-sk.dts which includes the former.
Fixes: afb074d9e26c ("arm: dts: k3-am69-sk: Add r5 specific dt support")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Since commit [1] spl_enable_dcache is no more available and,
at the same time, by enabling instruction cache, boot time is reduced.
[1] 536d0d5eef24 ("arm: k3: Enable instruction cache for main domain SPL")
Upstream-Status: Inappropriate
Commit [1] is already upstreamed. am62p5 and j784s4 were introduced
afterwards and they are using the new function.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
|
|
The maximum frequency of the A53 CPU on the AM62 depends on the speed
grade of the SoC. However, this value is hardcoded in the DT for all
AM62 variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency based on its speed grade.
Upstream-Status: Backport [5ed961094d456d03c481d2bf751f6eeb06c1bada]
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
|
|
AM62 SoC has multiple speed grades. Add function to return max A53 CPU
frequency based on grade. Fastest grade's max frequency also depends on
PMIC voltage, to simplify implementation use the smaller value.
Upstream-Status: Backport [ba26524cad98aa70913afb7a2436949ac14c3b41]
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
|
|
During the boot, the EFI loader maps the memory from ram_top to ram_end
as EFI_BOOT_SERVICES_DATA. When LMB does boot_fdt_add_mem_rsv_regions()
to OPTEE, TFA, R5, and M4F DMA/memory "no-map" for the kernel it produces
the following error message:
ERROR: reserving fdt memory region failed (addr=9cb00000 size=100000 flags=4)
ERROR: reserving fdt memory region failed (addr=9cc00000 size=e00000 flags=4)
ERROR: reserving fdt memory region failed (addr=9da00000 size=100000 flags=4)
ERROR: reserving fdt memory region failed (addr=9db00000 size=c00000 flags=4)
ERROR: reserving fdt memory region failed (addr=9e780000 size=80000 flags=4)
ERROR: reserving fdt memory region failed (addr=9e800000 size=1800000 flags=4)
To avoid this, don't flag with EFI_BOOT_SERVICES_DATA the memory from
ram_top to ram_end by the EFI loader.
Upstream-Status: Backport [3206b77c844c7f2d85e9154982f6ef9d72adaab6]
Related-to: ELB-5326
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
|
|
The maximum DDR RAM size stuffed on the Verdin AM62 is 2GB,
correct the memory node accordingly.
Commit 3610dbfc37e3 ("ram: k3-ddrss: Set SDRAM_IDX using device private
data, ddr_ram_size") now evaluates the device tree property and limits
DDR access to the specified size. Thus set the maximum stuffed size in
the dts corresponding to what is set in CFG_SYS_SDRAM_SIZE.
If CFG_SYS_SDRAM_SIZE is bigger than what is set in the device tree
SPLs and U-Boot freeze when probing for the DDR size.
Upstream-Status: Pending
The R5 dtb memory node is only needed in downstream TI U-Boot.
All mainline AM62 boards do not set the node, when said commit gets
upstreamed we can follow the pattern TI adds the node to the dtb.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
The maximum DDR RAM size stuffed on the Verdin AM62 is 2GB,
correct the memory node accordingly.
Commit 3610dbfc37e3 ("ram: k3-ddrss: Set SDRAM_IDX using device private
data, ddr_ram_size") now evaluates the device tree property and limits
DDR access to the specified size. Thus set the maximum stuffed size in
the dts corresponding to what is set in CFG_SYS_SDRAM_SIZE.
If CFG_SYS_SDRAM_SIZE is bigger than what is set in the device tree
SPLs and U-Boot freeze when probing for the DDR size.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240320142937.2028707-1-max.oss.09@gmail.com/]
Submitted to the linux kernel. Upstream U-Boot will get it through the
regular sync with Linux.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Replace all the fsstub occurences with tifsstub to avoid new
terminology and resulting confusion.
This follows commit 57f1e97afad ("arm: dts: k3-*: s/fsstub/tifsstub/")
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
|
|
Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Upstream-Status: Backport [3ef977e085767df31e42262f15837a66558052db]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Move the DM entry in tispl.bin FIT image from default fetching an
external blob entry to fetching using ti-dm entry type. This way, the
DM entry will be populated by the TI_DM pathname if provided. Else it
will resort to the ti-dm.bin file.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
|
|
J7200 has SR1.0 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR1.0 and HS-FS SR1.0 so
add support for them.
Reported-by: Suman Anna <s-anna@ti.com>
Reported-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so
add support for them.
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
|
|
Enable microtips mf101hie OLDI panel and link it with DSS ports to
enable splash screen on AM62x LP SK.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
|
|
commit 2764be4345 ("remoteproc: uclass: Add methods to load
firmware to rproc and boot rproc") selects FS_LOADER in Kconfig
and this breaks R5 build for some defconfigs across multiple platforms.
Enabling CONFIG_SPL_FS_LOADER does not help for all cases.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The default DM firmware path is non-optional as of now. Make it
optional so that users that choose to provide DM via TI_DM argument
instead of BINMAN_INDIRS can do so without build errors.
Cc: Chirag Shilwant <c-shilwant@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Chirag Shilwant <c-shilwant@ti.com>
|
|
Move bus-width property to *main.dtsi, above the OTAP/ITAP
delay values. While there is no error with where it is
currently at, it is easier to read the MMC node if the
bus-width property is located above the OTAP/ITAP delay
values consistently across MMC nodes.
Add missing bus-width DTS property for sdchi2 in k3-am62-main.
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Move ti,clkbuf-sel property above the OTAP/ITAP delay values.
While there is no error with where it is currently at, it is
easier to read the MMC node if ti,clkbuf-sel is located above
the OTAP/ITAP delay values consistently across MMC nodes.
Add missing ti,clkbuf-sel DTS property for sdhci0 in k3-am64-main.
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Remove DLL properties which are not applicable for soft PHYs
since these PHYs do not have a DLL to enable.
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Update MMC OTAP/ITAP values according to the datasheet
[0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Update MMC0/MMC1 OTAP/ITAP delay values according to the
datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97
for MMC1.
[0] https://www.ti.com/lit/ds/symlink/am62a7.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Update MMC0/MMC1 OTAP/ITAP values according to the datasheet
[0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1.
Move ITAPDLY values after OTAPDLY values to make MMC
nodes more uniform across devices.
[0] https://www.ti.com/lit/ds/symlink/am6442.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap
values according to the datasheet[0], Refer to Table 7-97.
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Judith Mendez <jm@ti.com>
|
|
Nothing much has changed between the versions of the emif output. Some
changes to the PHY_PAD_CAL_IO_CFG_0, PHY PAD RST DRIVE, and
PHY_CAL_CLK_SELECT_0 should add some minor stability improvements.
Nonetheless, update to the latest characterization developments.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
On AM69 board, build image was going beyond wrt defined
offsets.
So increasing offset for eMMC and OSPI boot. Along with
update in corresponding device tree.
Cc: Neha Francis <n-francis@ti.com>
Cc: Vaishnav Achath <vaishnav.a@ti.com>
Cc: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Beleswar Padhi <b-padhi@ti.com>
|
|
AVS driver was getting probed with base device tree, which
leads i2c of derivative board (AM68) in bad state.
Moving AVS probe after detection of right device tree.
Fixes: eaa184009775 ("arm: k3: j721s2: Enable AVS")
Reported-by: Minas Hambardzumyan <minas@ti.com>
Cc: Manorit Chawdhry <m-chawdhry@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
|
|
The output from the emif tool hasn't changed for a while now, however
there is still a difference from what we use.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
The output from the emif tool hasn't changes in a long while however
there are some differences. Update to these latest settings.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
After a little debugging on the am62px some of these values will need to
be changed. Update to these new values to improve stability at higher IO
voltages.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
After a little bit of debugging and characterization at different IO
voltages, some of these values will need to change. Update to these
latest settings to improve stability at higher IO voltages.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
ICSSG1 provides dual Gigabit Ethernet support.
Add ICSSG1 ethernet node to am64x device tree.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
derived from either of the IP instance's ICSSG_IEP_GCLK or from another
internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG
instances. The IEP clock is currently configured to be derived
indirectly from the ICSSG_ICLK running at 250 MHz.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dts
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
There are a few missing registers ranges in the udmap nodes
need to properly setup DMA for the am65x.
A fix has been added to the Linux kernel [0] to add these ranges and
merged. To keep DMA operational until the next DT sync from Linux, these
ranges were added to the *-u-boot.dtsi in the upstream u-boot [1].
Porting these DMA changes to ti-u-boot as these are needed for ICSSG
Ethernet driver to work.
And additional config register was added to the ringacc node in upstream
u-boot as part of DT sync from linux 6.7-rc1 [2]. Porting those changes
as well to ti-u-boot as those are also needed for ICSSG Ethernet driver to
work.
[0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com
[1] https://source.denx.de/u-boot/u-boot/-/commit/5e00547e583f6d4349f3908d3491bf6ce0a8818c
[2] https://source.denx.de/u-boot/u-boot/-/commit/4dbdc84754ea2ad392ef7328da6d429cd8fd3c0a
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
|
|
Update the USB0, USB1 nodes and enable them.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
Enable probing of AVS node in R5 SPL.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
|
