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Drive CTRL_SLEEP_MOCI# high at boot (A53 SPL) using a GPIO hog, this
signal may be used to control some power-rails on the carrier board,
therefore it should be set to high when the module is booting.
To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.
Upstream-Status: Pending
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Change memory configurations to operate at temperature of 95 degrees.
Currently, dynamic adaptation of temperature related timings is not
supported [1] so the config is for the worst timings.
It is possibile to do so because LPDDR4 devices are refreshed properly
if the memory controller issues REFRESH commands with same or *shorter*
refresh period than reported by MR4 OP[2:0] which depend upon device
temperature.
Configuration is output from SysConfig [2] web tool, currently at version
00.09.08, starting from previous configuration while modifying
these temperature related properties:
- Operating Temperature Range to "-40C to 95C"
- tREFIab (ns) to 1950
- tREFIpb (ns) to 244
- tRASmax (ns) to 17550
[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1234907/am625-lpddr4-configuration-and-operating-temperature
[2] https://dev.ti.com/sysconfig
Upstream-Status: Pending
Series [3] already send for review with the previous configuration,
we'll send afterward or update it in case a V2 is needed.
[3] https://lore.kernel.org/all/20230607120639.82087-1-marcel@ziswiler.com/
Related-to: ELB-5200
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Disable sdhci2 used for the on-module Wi-Fi as distroboot trying to
unsuccessfully initialize it during boot is later causing downstream
Linux to hang during boot.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Fix raw eMMC boot mode detection. Patch from TI [1].
[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1204131/faq-a53-boot-binary-tispl-bin-loading-error-when-bootmode-7-0-in-emmc-boot-mode-on-am62x
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Integrate Ethernet support.
Note: Due to U-Boot not support pinctrls in the cpsw3g_midio node they
were all added to the cpsw3g node. And due to U-Boot currently not
supporting Ethernet PHY reset-gpios we just GPIO hog it.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Currently only the SPL running on the R5 has a clock driver. As a
workaround therefore move the assigned-clock stuff required for our
ETH_25MHz_CLK from the cpsw3g_mdio node of the regular device tree to
the a53@0 node of the R5 device tree.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Fix second mux option of clkout0 which should really be
DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10
rather than twice the same according to [1].
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device
Upstream-Status: Pending
Despite the disclaimer discouraging hand editing this file due to it
being auto generated, it is buggy. This issue has been reported to TI.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Migrate and sync to using Linux kernel (albeit still downstream) device
trees.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Merge TI U-Boot RC Release 08.06.00.007
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Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.08 generates which supports
bit swizzle configuration. From its README:
v9.08
-added automatic change of RL, WL and nWR when frequency is changed
-added DQ swizzle and byte swap configuration flexibilty for AM62x/AM62A LPDDR4
-PHY_CAL_CLK updated divider values for higher frequencies
-CS ODT fix bug introduced in previous release
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Add the BP_C bit position of the LFXOSC_CTRL Register.
This allows to bypass the crystal oscillator when providing
the clock from an external source.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.05 generates. From its
README:
v9.04:
-changed wrlvl_delay_early_threshold=0x100 to allow write leveling
to complete successfully for wider array of layouts
-add cmm output
-LPDDR4: phy_rddqs_latency_adjust changed to 0 default
recommendation (this value gets optimized during training)
-LPDDR4: optimized training loops to support 1 operating frequency
-LPDDR4/DDR4: optimized IO calibration configuration based on
operating frequency
-LPDDR4/DDR4: optimized internal calibration clock based on
operating frequency
-LPDDR4: changed default MR22 ODTE-CS=1
-LPDDR4: changed rx_ctle_cs default to No Boost
-AM62x dual rank support
-updated to use sysconfig v1.15
-public release for AM62A LPDDR4 support
v9.05:
-cleaned up supported frequencies
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Drop SKEVM specific stuff.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Add alias for M4F remoteproc and carveout memories for IPC.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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AM62x device has a M4F core in mcu power domain. The the M4F core is primarily
intended for safety applications and can be isolated from the rest of the SoC.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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HS-FS is technically a GP device wrt development flow, kernel images can
be either signed and packaged as a fitImage or can be regular Image and
dtbs loaded separately.
Default to legacy booting mechanism for kernel ie Image and dtb are
individual files and not necessarily signed. This provides widest
compatibility and aligns with ease of use.
For HS-SE though, keep fitImage as default though as one expects to boot
signed images on secure devices.
Users can force fitImage boot by setting boot_fit 1 on HS-FS too.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Currently, code doesn't take into account the fact that user may have
overriden boot_fit value via env using saveenv.
Check if boot_fit is already set before overriding based on SoC type.
This allows users to boot signed fitImage or regular kernel Image and
dtbs consistently without needing to stop at U-Boot prompt and
overriding the variable each time.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
V1.0A module. They are strapped to boot from their on-module eMMC.
U-Boot supports booting from the on-module eMMC, or, via separate
verdin-am62_r5_usbdfu_defconfig from USB DFU based recovery mode.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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The Colibri PXA270 has been end-of-life since quite a while and would
require more and more maintenance (e.g. DM conversions).
Upstream-Status: Backport [fc102c87c11dfd52039326534ff831d3edd8340d]
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Drop Apalis iMX8X platform as it never left sample state and is no
longer supported.
Upstream-Status: Backport [47bcc0d056aa243a31d2a1edb44bdcd155f5335b]
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Add initial support for device tree that runs on R5.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
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Two carveout reserved memory nodes each have been added for each of the
R5F and C71x remote processor devices/DSP/DSPs within both the MCU and
MAIN domains. These nodes are assigned to the respective rproc device
nodes as well. The first region will be used as the DMA pool for the
rproc device, and the second region will furnish the static carveout
regions for the firmware memory.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
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AM69 Starter Kit is a single board designed for TIâs AM69 SoC.
TIâs AM69 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications,
autonomous mobile robot and edge AI applications. The SOC comprises
of Cortex-A72s in dual clusters, lockstep capable dual Cortex-R5F MCUs,
Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP)
and multiple vision assist accelerators, Depth and Motion Processing
Accelerators (DMPAC), Deep-learning Matrix Multiply Accelerator(MMA)
and C7x floating point vector DSP
AM69 SK supports the following interfaces:
* 32 GB LPDDR4 RAM
* x1 Gigabit Ethernet interface
* x1 USB 3.1 Type-C port
* x2 USB 3.1 Type-A ports
* x1 PCIe M.2 M Key
* x1 PCIe M.2 E Key
* 512 Mbit OSPI flash
* x2 CSI2 Camera interface
* 40-pin Raspberry Pi header
* 50-pin ENET Header
Add initial support for the AM69 SK board.
Design Files: https://www.ti.com/lit/zip/SPRR466
TRM: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
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Add support for selecting DTB from FIT based on the board name
read from EEPROM. This facilitates the use of single defconfig
for EVM and SK.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
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AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.
Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].
[1] : https://www.ti.com/lit/zip/spruj16
Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Add support for AM62Q NAND card: X8 NAND EXPANSION
BOARD card (PROC143E1) for AM62x LP SK board. NAND
has partitions for different boot components as
below:
0x000000000000-0x000000200000 : "NAND.tiboot3
0x000000200000-0x000000400000 : "NAND.tispl
0x000000400000-0x000000600000 : "NAND.tiboot3.backup
0x000000600000-0x000000a00000 : "NAND.u-boot
0x000000a00000-0x000000a40000 : "NAND.u-boot-env
0x000000a40000-0x000000a80000 : "NAND.u-boot-env.backup
0x000000a80000-0x000040000000 : "NAND.file-system
Note, there is simply not enough SRAM to support
application of overlay and hence NAND addon card
is not modeled as overlay.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
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This adds GPMC and ELM nodes in preparation to
add GPMC NAND addon card support.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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Add clock and device data to enable GPMC NAND access at
R5 SPL support. This is needed to support booting out of
GPMC NAND device.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Regenerate clk and dev data with unused eMMC board
clocks removed which saves precious SRAM space.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Introduce an option of booting from GPMC NAND device
in primary bootmedia list.
Also, fix NAND BOOT device definition.
Fixes: e52197789d4 (arm: mach-k3: Introduce the basic files to support AM62)
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
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On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that
is present in above 64bit region. Open this up in bootloader to allow
Linux to access OSPI flashes in mmap mode.
Without this kernel will crash when accessing this region due to
firewall violations on HS-SE devices.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Judith Mendez <jm@ti.com>
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Updates to HyperBus calibration sequence requires the HBMC
config register region, include that in hbmc node.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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Updates to HyperBus calibration sequence requires the HBMC
config register region, include that in hbmc node.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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The u-boot SoC specific dtsi files are updated to align with Kernel.
Update the j784s4 evm DT files to accomodate those change made to the
dtsi files.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Tested-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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The u-boot DT files need to be in sync with kernel DT files.
Update the SoC specific DT files to match the label, node names and
add the missing nodes to be in sync with the kernel files.
The List of updates in the k3-j784s4-main.dtsi file:
* The nodes and child nodes of system-controller
* The node name of hwlock
* The nodes and child nodes of the main_cpsw0 and main_cpsw1
The List of updates in the k3-j784s4-mcu-wakeup.dtsi file:
* Label name of mcu_cpsw_port1
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Tested-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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AM62A SK has a W35 OSPI NAND connected to OSPI controller. Add DT nodes
for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Use more conventional naming scheme for NAND partitions
and enable listing of partitions in prompt.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.
The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.
With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.
The am62a qos files are auto generated from the k3 resource partitioning
tool.
Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, with the register descriptions
explanined under the "System Interconnect Registers" in "AM62A TRM
Registers 1" section.
[1] AM62A Tech Ref manual: https://www.ti.com/lit/zip/spruj16
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
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Add initial support for device tree that runs on R5.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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The SK architecture comprises of baseboard and a SOM board. The
AM68 Starter Kit's baseboard contains most of the actual connectors,
power supply etc. The System on Module (SoM) is plugged on to the base
board. Therefore, add support for peripherals brought out in the base
board.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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AM68 Starter Kit (SK) is a low cost, small form factor board designed
for TIâs AM68 SoC. TIâs AM68 SoC comprises of dual core A72, high
performance vision accelerators, hardware accelerators, latest C71x
DSP, high bandwidth real-time IPs for capture and display. The SoC is
power optimized to provide best in class performance for industrial
applications.
AM68 SK supports the following interfaces:
* 16 GB LPDDR4 RAM
* x1 Gigabit Ethernet interface
* x1 USB 3.1 Type-C port
* x2 USB 3.1 Type-A ports
* x1 PCIe M.2 M Key
* 512 Mbit OSPI flash
* x2 CSI2 Camera interface (RPi and TI Camera connector)
* 40-pin Raspberry Pi GPIO header
SK's System on Module (SoM) contains the SoC, PMIC, DDR and OSPI flash.
Therefore, add support for the components present on the SoM.
Schematics: https://www.ti.com/lit/zip/SPRR463
TRM: http://www.ti.com/lit/zip/spruj28
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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Although the board_init_f API initialises the SoC, the API name is
incorrectly specified and misleads the functionality. This file should
only include k3-specific functionality. Change the API's name to something
more K3-specific and separate the function to make it more modular.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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Add support for USB controllers and enable the USB to boot via DFU
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Enable eMMC node to support booting from on board eMMC
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add sdhci0 node which is a 8bit MMC interface to support eMMC/SD/SDIO
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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ROM supports RAW as well as FS based boot in eMMC mode. Add support to
distinguish the same and proceed accordingly for loading next stages.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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the macro for the boot data location from rom is misspelled. fix it
Signed-off-by: Bryan Brattlof <bb@ti.com>
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AM62A SoC has a C71x DSP and R5F core in main voltage domain and
another R5F core in wakeup domain. The IPC between the R5F, C71x and
A53 processors is through shared memory and mailboxes.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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AM62A SoC has a single R5F core in MCU voltage domain.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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