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2020-10-29sandbox: make SDL window resizableHeinrich Schuchardt
Without resizing the SDL window showed by ./u-boot -D -l is not legible on a high resolution screen. Allow resizing the window Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
2020-10-28test: Add tests for the multiplexer frameworkJean-Jacques Hiblot
Provide tests to check the behavior of the multiplexer framework. Two sets of tests are added. One is using an emulated multiplexer driver that can be used to test basic functionality like select, deselect, etc. The other is using the mmio mux which adds tests specific to it. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-26riscv: fu540: dts: Correct reg size of clint nodePragnesh Patel
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson
Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson
This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Move Andes PLMT driver to drivers/timerSean Anderson
This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: k210: Reduce DMA block sizeSean Anderson
Although the max DMA size supported by the hardware register is 22 bits (or 4M), the Linux driver for this device only supports transfers of up to 2M. On a device with 8M total memory, I don't think it will make too much of a difference. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Only enable OF_BOARD_FIXUP for S-ModeSean Anderson
It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE. OF_SEPARATE may indicate that the user wishes U-Boot to use a different device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may also indicate that the device tree which would be obtained via OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this latter case, enabling OF_BOARD_FIXUP will result in corruption of the device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode. Fixes: 1c17e55594a394ced7de88d91be294eaf8c564c1 Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-10-23Revert "arch: arm/xen: add putc() for debugging"Tom Rini
This reverts commit 3a51b2a2c3cedc0d2a9ce981b8e00ab8cefcb6b7. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23armv8: layerscape: don't remove crypto node if just partially disabledMichael Walle
On all newer Layerscape SoCs, only the export-controlled ciphers of the crypto module are disabled on non-E parts. Thus it doesn't make sense to completely remove the node. Linux will figure out what is there and what is not. Just remove it for older SoCs, where the module is indeed completely disabled on non-E parts. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23board: kontron: add sl28 supportMichael Walle
Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan
As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor
In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-22Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- sun8i emac changes (Andre) - SCP firmware (Samuel)
2020-10-22arch: arm/xen: add putc() for debuggingAKASHI Takahiro
This new function, xen_debug_putc(), is intended to be used to enable CONFIG_DEBUG_UART on xen guest. Please note that the underlying functionality in Xen is available only when Xen is configured with !NDEBUG but is much simpler than a generic HYPERVISOR_console_io(). Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22reset: ast2500: Use SCU for reset controlChia-Wei, Wang
The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-22IPQ40xx: Add PRNG supportRobert Marko
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22IPQ40xx: Add support for MDIORobert Marko
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22IPQ40xx: Add SPI supportRobert Marko
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22km: fix license string and compatible stringsHolger Brunck
As the ownership is now Hitachi Power Grids, change the license string and adapt the compatible string in DTS files. For kmeter1.dts we change it to "keymile,KMETER1" for now, as this is then compliant with what is submitted to the linux kernel. All other boards don't have a upstreamed version in linux mainline. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> CC: Heiko Schocher <hs@denx.de> CC: Marek Vasut <marex@denx.de> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-10-22timer: Return count from timer_ops.get_countSean Anderson
No timer drivers return an error from get_count. Instead of possibly returning an error, just return the count directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22Merge branch '2021.01-rc' of https://github.com/lftan/u-bootTom Rini
- fix Gen5 enable of EMAC via FPGA
2020-10-22sunxi: binman: Add support for including SCP firmwareSamuel Holland
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a System Control Processor, or SCP. ARM Trusted Firmware (ATF) communicates with the SCP over SCPI to implement the PSCI system suspend, shutdown and reset functionality. Currently, SCP firmware is optional; the system will boot and run without it, but system suspend will be unavailable. Since all communication with the SCP is mediated by ATF, the only thing U-Boot needs to do is load the firmware into SRAM. The SCP firmware occupies the last 16KiB of SRAM A2, immediately following ATF. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22sunxi: binman: Update FIT component descriptionsSamuel Holland
Since commit d879616e9e64 ("spl: fit: simplify logic for FDT loading for non-OS boots"), the SPL looks at the "os" properties of FIT images to determine where to append the FDT. The "os" property of the "firmware" image also determines how to execute the next stage of the boot process, as in 1d3790905d9c ("spl: atf: introduce spl_invoke_atf and make bl31_entry private"). For this reason, the next stage must be specified in "firmware", not in "loadables". To support this additional functionality, and to properly model the boot process, where ATF runs before U-Boot, add the "os" properties and swap the firmware/loadable images in the FIT image. Since this description was copied as an example in commit 70248d6a2916 ("binman: Support generating FITs with multiple dtbs"), update those examples as well for correctness and consistency. Acked-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22sunxi: binman: Use a macro for the BL31 load addressSamuel Holland
This consolidates the SoC-specific part at the top of the file to avoid cluttering it up with preprocessor conditions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22sunxi: binman: Provide a default BL31 filenameSamuel Holland
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use binman"), if the BL31 environment variable was not defined, the firmware would be loaded from a file "bl31.bin" in the current directory. Restore that behavior by providing that as the default filename in case no entry arg is provided, which will be the case if the environment variable is unset. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22sunxi: binman: Fix spacing between nodesSamuel Holland
Nodes should have a blank line separating them from sibling nodes and properties. Add the necessary lines. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22sunxi: make V3s DRAM initialization more properIcenowy Zheng
Previously, because we have no source code about the DRAM initialization of V3s and missing some configurations (delays and MBUS QoS info), our V3s DRAM initialization sequence is hacked from the H3 one. As the SDK shipped with PineCube contains source code for V3s libdram, we can retrieve these information from it and tweak some other magic bits. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21stm32mp: stm32prog: accept device without partitionPatrick Delaunay
When partitions are not available on a device the command stm32prog raises an error but a device can have no partition to check in init_device() and the command need to continue to the next part_id. This patch correct an issue for ram0 target, when block_dev and mtd are NULL. For example with the simple flashlayout file: Opt Part Name Type Device Offset Binary - 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32 - 0x03 ssbl Binary none 0x0 u-boot.stm32 P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb Fixes: ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21arm: stm32: cleanup arch gpio.hPatrick Delaunay
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21stm32mp: limit size of cacheable DDR in pre-reloc stagePatrick Delaunay
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21arm: socfpga: fix Gen5 enable of EMAC via FPGARalph Siemsen
An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- Assorted R-Car Gen3 updates
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774E1 SoCBiju Das
Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774B1 SoCBiju Das
Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: dts: mt8512: add usb related nodesChunfeng Yun
Add usb, usb phy, and fixed regulators nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-19ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
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