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Add the BP_C bit position of the LFXOSC_CTRL Register.
This allows to bypass the crystal oscillator when providing
the clock from an external source.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.05 generates. From its
README:
v9.04:
-changed wrlvl_delay_early_threshold=0x100 to allow write leveling
to complete successfully for wider array of layouts
-add cmm output
-LPDDR4: phy_rddqs_latency_adjust changed to 0 default
recommendation (this value gets optimized during training)
-LPDDR4: optimized training loops to support 1 operating frequency
-LPDDR4/DDR4: optimized IO calibration configuration based on
operating frequency
-LPDDR4/DDR4: optimized internal calibration clock based on
operating frequency
-LPDDR4: changed default MR22 ODTE-CS=1
-LPDDR4: changed rx_ctle_cs default to No Boost
-AM62x dual rank support
-updated to use sysconfig v1.15
-public release for AM62A LPDDR4 support
v9.05:
-cleaned up supported frequencies
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Drop SKEVM specific stuff.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
V1.0A module. They are strapped to boot from their on-module eMMC.
U-Boot supports booting from the on-module eMMC, or, via separate
verdin-am62_r5_usbdfu_defconfig from USB DFU based recovery mode.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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The Colibri PXA270 has been end-of-life since quite a while and would
require more and more maintenance (e.g. DM conversions).
Upstream-Status: Backport [fc102c87c11dfd52039326534ff831d3edd8340d]
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Drop Apalis iMX8X platform as it never left sample state and is no
longer supported.
Upstream-Status: Backport [47bcc0d056aa243a31d2a1edb44bdcd155f5335b]
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.
The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.
With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.
The am62a qos files are auto generated from the k3 resource partitioning
tool.
Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, with the register descriptions
explanined under the "System Interconnect Registers" in "AM62A TRM
Registers 1" section.
[1] AM62A Tech Ref manual: https://www.ti.com/lit/zip/spruj16
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
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Add initial support for device tree that runs on R5.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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The SK architecture comprises of baseboard and a SOM board. The
AM68 Starter Kit's baseboard contains most of the actual connectors,
power supply etc. The System on Module (SoM) is plugged on to the base
board. Therefore, add support for peripherals brought out in the base
board.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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AM68 Starter Kit (SK) is a low cost, small form factor board designed
for TIâs AM68 SoC. TIâs AM68 SoC comprises of dual core A72, high
performance vision accelerators, hardware accelerators, latest C71x
DSP, high bandwidth real-time IPs for capture and display. The SoC is
power optimized to provide best in class performance for industrial
applications.
AM68 SK supports the following interfaces:
* 16 GB LPDDR4 RAM
* x1 Gigabit Ethernet interface
* x1 USB 3.1 Type-C port
* x2 USB 3.1 Type-A ports
* x1 PCIe M.2 M Key
* 512 Mbit OSPI flash
* x2 CSI2 Camera interface (RPi and TI Camera connector)
* 40-pin Raspberry Pi GPIO header
SK's System on Module (SoM) contains the SoC, PMIC, DDR and OSPI flash.
Therefore, add support for the components present on the SoM.
Schematics: https://www.ti.com/lit/zip/SPRR463
TRM: http://www.ti.com/lit/zip/spruj28
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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Although the board_init_f API initialises the SoC, the API name is
incorrectly specified and misleads the functionality. This file should
only include k3-specific functionality. Change the API's name to something
more K3-specific and separate the function to make it more modular.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
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Add support for USB controllers and enable the USB to boot via DFU
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Enable eMMC node to support booting from on board eMMC
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add sdhci0 node which is a 8bit MMC interface to support eMMC/SD/SDIO
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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ROM supports RAW as well as FS based boot in eMMC mode. Add support to
distinguish the same and proceed accordingly for loading next stages.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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the macro for the boot data location from rom is misspelled. fix it
Signed-off-by: Bryan Brattlof <bb@ti.com>
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AM62A SoC has a C71x DSP and R5F core in main voltage domain and
another R5F core in wakeup domain. The IPC between the R5F, C71x and
A53 processors is through shared memory and mailboxes.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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AM62A SoC has a single R5F core in MCU voltage domain.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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AM62A SoC has 4 mailbox clusters and a C71x DSP in main voltage
domain. The mailboxes are used for interprocessor communications
between the remote processors (R5F, C71x and A53) and host processor.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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Introduce the Direct Memory Access and Ethernet device tree nodes needed
by uboot's ethernet drivers.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Starting with v08.05.01 TIFS, HSM SRAM access is restricted to only the
DM firmware and SMS cores meaning the A53 SPL and U-Boot will no longer
be able to access these parts of SRAM.
Unfortunately there are two data structures located in the HSM SRAM the
A53's boot-loaders will need and now must be relocated by the R5 SPL.
1. The boot index from ROM, indicating whether ROM booted from the
primary vs backup boot media.
2. And the Board EEPROM data scratch pad.
The EXTENDED BOOT INFO, indicating which images ROM loaded is not needed
by the A53 SPL and is now limited to the R5 SPL.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the auto-generated clock tree and power domain data needed to
attach the am62a into the power-domain and clock frameworks of uboot
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the mach-k3 files needed to properly boot TI's am62a SoC
family of devices
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the base dts files needed for u-boot or to augment the
linux dtbs for use in the u-boot-spl and u-boot binaries
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Introduce the basic am62a7 SoC dtbs from the linux kernel along with the
new am62a specific pinmux definition that we will use to generate the
dtbs for the u-boot-spl and u-boot binaries
Co-developed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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During R5 SPL stage OC RAM is unavailable hence use store EEPROM data in
HSM SRAM and use OCRAM in case of A53 SPL/U-Boot (as HSM SRAM is
unusable at this stage).
This unblocks HS-SE boot on AM62
Fixes: 2a54311a12 ("mach-k3: am625_init: Avoid HSM SRAM accesses from A53 SPL/U-Boot")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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This virtual clock mux configuration enables the use of dynamic frequency
scaling on A72 clock ID 202 by setting up the required register.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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This virtual clock mux configuration enables the use of dynamic frequency
scaling on A72 clock ID 202 by setting up the required register.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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With SPI_LOAD disabled, below warning is seen
arch/arm/mach-k3/sysfw-loader.c:378:8: warning: unused variable âsysfw_spi_baseâ [-Wunused-variable]
378 | void *sysfw_spi_base;
| ^~~~~~~~~~~~~~
Fix the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Class U1 UHS SD cards are failing to boot at u-boot. Renable UHS
related DT nodes given that driver and OTAP and ITAP values are
now updated. Enable UHS modes and voltage switching by default
for by enabling the respective nodes in the device tree, remove
sdhci-caps-mask in sdhci1 node and add sdhci2 node in device tree.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
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UHS Class U1 sd-card are failing to boot due to incorrect
OTAP/ITAP delay select values. Update OTAP and ITAP delay
select values for various speed modes. For sdhci0 update
OTAP delay values for ddr52 & HS200 and add ITAP delay for
legacy & mmc-hs in dt nodes. For sdhci1 & sdhci2, update
OTAP & ITAP delay select recommended as in RIOT for various
speed modes.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
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Starting with v08.05.01 TIFS, HSM SRAM access is restricted to DM R5 and
SMS Cores only, A53 SPL/U-Boot won't be able to access those SRAMs.
There are three data structures in the HSM SRAM that A53 SPL/U-Boot make
use of which needs relocation:
1. Boot index info from ROM indicating whether ROM booted from primary
vs secondary media. This is now relocated to On Chip RAM by R5 SPL
2. EXTEND BOOT INFO which indicates images loaded by ROM, this info is
not needed by A53 SPL and thus is limited to R5 SPL usage
3. Board EEPROM data scratch pad, which is now moved to On Chip RAM
Co-developed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Tested-by: Judith Mendez <jm@ti.com>
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In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.
CC: Apurva Nandan <a-nandan@ti.com>
CC: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Moving forwared, DM firmware will no longer mess with the MAIN_PLL3.
This means we (uboot) will need to manually set this PLL to 2GHz in
order order for the CPSW HSDIV to have the correct 250MHz output.
CC: Jonathan Bergsagel <jbergsagel@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The data TI's firmware teams use to develop their releases, and the
source for these files, are constantly in motion. This churn eventually
causes the ordering of the clock tree in the WKUP SPL to change without
having any functional change to the driver.
So, to enable later patches wishing to make updates to this stripped
down clock trees, reorder the clocks to match the v08.05.01 release.
There are no functional changes.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Move start of eeprom address from on chip SRAM to HSMRAM
This Macro is being used to verify that we can write/read to EEPROM
OCSRAM is firewalled by ROM, so before TIFS opens up that
firewall, we can't access it. Because of this, we were getting
firewall exception in r5 core
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
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Added device data for main_uart5 in dev-data.c for J784S4. Now,
main_uart5 will be powered on in SPL while booting the J784S4 soc and
thus can be used at any point of time.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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Added support for main_uart5 clock in clk-data.c for J784S4. Now,
main_uart5 will be turned on in SPL while booting the J784S4 soc and
thus can be used at any instance of of time.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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Added device data for main_uart5 in dev-data.c for J721S2. Now,
main_uart5 will be powered on in SPL while booting the J721S2 soc and
thus can be used at any point of time.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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Added support for main_uart5 clock in clk-data.c for J721S2. Now,
main_uart5 will be turned on in SPL while booting the J721S2 soc and
thus can be used at any instance of of time.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
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Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
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This isn't strictly needed as these firewalls should all be disabled on
GP, but it also doesn't hurt, so do this unconditionally to remove this
use of CONFIG_TI_SECURE_DEVICE.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[ extended to other platform (j721s2) ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
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Change GTC and CPTS clock parents on J784S4 to main pll0, hsdiv6 from
pll3, hsdiv1. This is because pll3, hsdiv0 sources cpsw rgmii and this
needs to be at 250MHz. And on the other hand GTC clock needs to be at
200 MHz. Since it is not possible to program the hs dividers for 250
200 MHz from same VCO frequency, move GTC and CPTS clock parents to
main pll0, hsdiv6.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Acked-by: Apurva Nandan <a-nandan@ti.com>
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On J784S4 SoC, GTC and CPTS clock parents can be selected from either
main pll0 HS divisor6 or main pll3 HS divisor1. The GTC clock needs
to be at 200 MHz and this decides the HS divisor and VCO clock frequency
to be used. Since the main pll0 and pll3 also source clocks for other
peripherals and may need specific frequency the VCO of the plls need
to be preset to a default value. On J784S4 the default VCO freqeuncy
to satisy GTC and othe peripherals on pll0 is 2000 MHz.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Acked-by: Apurva Nandan <a-nandan@ti.com>
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Implement overrides for spl_spi_boot_bus() lookup function according
to bootmode selection, so as to support both QSPI and OSPI boot using
the same build.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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Enable OSPI1 instance for J784S4 EVM in R5 SPL and A72 SPL,U-Boot.
OSPI1 instance has mt25qu512a QSPI flash connected on J784S4 EVM.
This commit enables the instance and adds the necessary DT entries
and pre-relocation properties to enable the OSP1 controller and
instantiate mt25qu512a flash.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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Fix the serdes0 node to support USB3 correctly
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: Matt Ranostay <mranostay@ti.com>
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HS400 is not supported for SDHCI0(eMMC). Kernel dts is not having the
mmc-hs400-1_8v property while the U-Boot counterpart is still having
that.Updated the speed modes supported to HS200 and their itap delay
values for MMCSD subsystems in U-boot.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
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When building tispl.bin for AM62x we depend on the _HS SPL and DTB files
now as we build the secure configuration by default.
Add this dependency here.
Fixes: 30457e61bc0b ("arm: k3: config_secure.mk: Add tispl.bin to secure device builds")
Reported-by: LCPD Autobuilder <lcpd_integration@list.ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
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When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.
Signed-off-by: Andrew Davis <afd@ti.com>
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