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2022-07-18MLK-25979-3 imx8ulp: xrdc: Set MRC4/5 for access DDR from A35 and APD PERYe Li
iMX8ULP A1 S400 ROM will remove the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-2 imx8ulp: soc: Limit the eMMC ROM API workaround to A0.1 partYe Li
Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-1 imx8ulp: soc: Get chip revision from SentinelYe Li
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18LFU-361-3 arm: dts: imx93: move usb i2c devices to i2c3Clark Wang
According to the board design change, move USB i2c devices to lpi2c3 bus. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-361-2 imx9: clock: correct i2c clock rootClark Wang
The root clock used in imx_get_i2cclk() is incorrect. Change it to LPI2C1_CLK_ROOT. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25975 imx93: Update pinctrl header file in DTS and archYe Li
The DTS imx93-pinctrl.h in u-boot is not latest. It uses wrong select input registers offset. So update this file to align with kernel. We also update imx93_pins in arch to add SION for all i2c and i3c SCL/SDA Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25898 ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25965-12 DTS: imx93-11x11-evk: Add nodes for MIPI DSI displayYe Li
Add nodes for MIPI DSI RM67199 panel and adv7535 DSI to HDMI card Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-11 DTS: imx93: Update imx93 DTSi for mediamix nodesYe Li
Sync iMX93 SoC DTSi with kernel for adding and updating nodes in mediamix Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-10 imx9: clock: Add mxs_set_lcdclk API and Frac PLL rateYe Li
Implement the mxs_set_lcdclk to select video PLL frequency according to pixel clock rate and set MEDIA_DISP_PIX_CLK_ROOT accordingly Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-9 video: adv7535: Update compatible stringYe Li
Change the compatible string from 7533 to 7535 to align with kernel Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25958 arm: dts: imx93: enable DM clock in SPL for i.MX93Alice Guo
Enable DM clock in SPL for i.MX93. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06MLK-25953-4 misc: s400_api: Use new command request definitionsYe Li
Remove legacy command definitions, change to use new ELE_xxx command request. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-3 imx: ahab: Move imx9 and imx8ulp AHAB support togetherYe Li
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since both of them use same sentinel ELE APIs Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-2 imx93: ahab: Get and decode AHAB eventsYe Li
For ahab_status command, support to get and decode AHAB events Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-1 s400_api: Add get_events APIYe Li
Add get_events API to retrieve any singular events that has occurred since the FW has started from sentinel Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25902-1 gpio: adp5585: update adp5585 gpio driverAlice Guo
The adp5585 used on i.MX93 has 10 GPIOs, so we update ADP5585_MAXGPIO, ADP5585_BANK and ADP5585_BIT. GPIO_x_DIR equals to 0 for input and 1 for output. Make corresponding changes in adp5585_get_function. Initialize plat->dat_out and plat->dir in adp5585_probe. Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFOPTEE-158 imx9: add OPTEE device tree node supportClement Faure
Add the FDT overlay support for OPTEE. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2022-07-06MLK-25904-1 arm: dts: imx93: add a per clock for LPUART1Alice Guo
When CLK is enabled, get_lpuart_clk_rate() needs to get a per clock of lpuart, so that add a per clock for lpuart1. Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-338-2 imx9: ahab: Fix lifecycle and remove debug codesYe Li
Update lifecycle decoding to get lifecycle from FSB LMDA status. Remove unused debug codes Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-337 imx9: Remove DDRMIX slice power cycleYe Li
When A55 boot, DDRMIX is default power on. It is not needed to do additional power off/on cycle to DDRMIX SRC slice. This power cycle was thought to resolve DDR PHY accessing issue, but actually the issue is caused by wrong DDR PLL setting which has been fixed. So remove the unnecessary power cycle. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-49 imx93_evk: Set ARM clock to 1.7GhzYe Li
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC to Overdrive voltage 0.9V Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-48 imx93_evk: Add iMX93 11x11 EVK board supportYe Li
Add board codes and defconfig for i.MX93 11x11 EVK board. Supported functions: UART, USB host/gadget/typc/pd, I2C, DDR, clock, SD/eMMC, eQoS, FEC, GPIO, IO Expander, PMIC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-47 arm: dts: Add iMX93 11x11 EVK supportYe Li
Add DTS file for i.MX93 11x11 EVK board. Support basic functions like: UART, USB, I2C, PMIC, FEC, eQoS, SD, eMMC, Sentinel MU, pinctrl. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-46 arm: dts: Add i.MX93 SoC DTSi fileYe Li
Add the DTSi file and DT header files for i.MX93 SoC Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFU-330-44 arm: imx9: Add i2c clock supportYe Li
Add clock interfaces to init and get lpi2c clock. By default we set lpi2c clock rate to 24Mhz. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-43 arm: imx9: Enable access to flexspi memory mapped spaceYe Li
Add flexspi memory mapped space to MMU table to allow read to flexspi NOR flash Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFU-330-42 ddr: imx9: enable Performance monitor counterYe Li
Add Kconfig for enabling reference events counter in DDRC performance monitor by default Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-41 ddr: imx: Add i.MX9 DDR controller driverYe Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-40 arm: imx9: clock: Add DDR clock supportYe Li
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-39 arm: imx9: Support multiple env storages at runtimeYe Li
Select env storages according to boot device at runtime Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-38 imx9: Support booting m33 from AcorePeng Fan
Add bootaux command to support on-demand booting M33 from u-boot. It kicks M33 via ATF by "bootaux 0x201e0000 0" Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-37 arm: imx9: Add M33 release prepare functionYe Li
To support on-demand booting M33 image from A core. SPL needs to follow M33 kick up sequence to release M33 firstly, then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick M33 to run. The prepare function also works around the M33 TCM ECC issue by clean the TCM. Also enable sentinel handshake and WDOG1 clock for M33 stop and reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-36 misc: s400_api: introduce ahab_release_m33_troutPeng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel release M33 trout and make sure M33 could boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-35 arm: imx9: Add MIX power initYe Li
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation of MIPI DSI/CSI, USBPHY after the power up. SPL should call the power init in its boot sequence before accessing above three MIX and USB. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-31 arm: imx9: Add gpio registers structureYe Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio driver Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-30 arm: imx93: Add SoC level support for USBYe Li
Add SoC level support for USB driver: 1. Add USB clock init 2. Clear USB PHY isolation Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-27 arm: imx9: Add SoC support for FEC and EQOSYe Li
Add SoC level support for FEC and eQOS controller. 1. Enable the FEC_QUIRK_ENET_MAC 2. Add clock interfaces for eQOS and FEC. eQoS and FEC work with REF CLK set to 250M. Because between CCM and ENET, there is a 1/2 divider 3. Set Wakeup AXI clock to 312.5Mhz, because FEC MDIO bus clock has a range for its clock divider (64 max), for 333Mhz AXI clock, it will overflow. 4. Add eQOS GPR registers, which is need to set RGMII and clock generation Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-23 misc: fuse: support to access fuse on i.MX93Alice Guo
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables for i.MX93. The offset address of FSB accessing OTP shadow registers is different between i.MX8ULP and i.MX93, so use macro to define the offset address instead of hardcode. Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFU-330-21 misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msgYe Li
Use more generic name for S40x msg structure Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-20 arm: imx9: Probe S4MU after u-boot relocationYe Li
Since the S4MU will not auto probe, need to probe it explicitly. arch_cpu_init_dm only probes it for board_f phase, also need to probe it again for board_r phase Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-19 arm: imx9: Get the chip revision through S400 APIYe Li
Update the get chip revision methond to use S400 API, also record other information like lifecycle and UID to global data. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-18 misc: S400_API: New API for FW status and chip infoYe Li
Add new API to get sentinel FW status and SoC chip info Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-17 arm: imx9: Add AHAB boot supportYe Li
Add AHAB driver for iMX9 to do authentication by calling sentinel API Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-16 arm: imx9: Add TRDC driver for TRDC initYe Li
Add TRDC driver to iMX9. The TRDC init splits to two phases: 1. Early init phase will release TRDC from Sentinel and open write permission to the memory where SPL image runs. Sentinel wiil set the memory to RX only after ROM authentication for the OEM closed part. 2. Init phase will configure TRDC to allow non-secure master to access DDR. So the peripherals can work in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-15 misc: S400_API: Update release RDC APIYe Li
To support more RDC instances on i.MX93, update API to latest definition. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-14 misc: s4mu: Support iMX93 with Sentinel MUYe Li
Add compatible string for iMX93 and add MU registers structure Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-13 misc: imx: S400_API: Move S400 MU and API to a common placeYe Li
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400 MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-12 arm: imx9: Add ROM API supportYe Li
Support the ROM API support on iMX9. Add relevant boot functions with ROM API used to get boot information Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-11 arm: imx9: Update the clock driver for PLL and CCMYe Li
Refactor the APIs for CCM components: root clock, GPR, LPCG. Add APIs for Int and Frac PLL control. Signed-off-by: Ye Li <ye.li@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-08 09:27:53 +0000