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2022-08-01LFU-373 imx8ulp: upower: Do not send AFFB enable message for A1Ye Li
On A1 part, upower ROM will default enable AFFB for APD/AVD/RTD before power on domains. We don't need to send the AFFB enable message any more. Actually enabling the AFFB of APD should happen during power mode switch which needs put APD to hold mode. It is hard to implement for boot, so upower ROM's implementation is necessary and simple. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-08-01imx8ulp: clock: Fix lcd clock algoLoic Poulain
The div loop uses reassign and reuse parent_rate, which causes the parent rate reference to be wrong after the first loop, the resulting clock becomes incorrect for div != 1. Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock") Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 85d0580e684c74dcb0a90aa0c010006cda40af44)
2022-07-31LFU-372-3 imx8ulp: Enable SCMI thermal for temperatureYe Li
Change from PMC thermal driver to SCMI thermal to get temperature, so that we can avoid TRDC access issue for PMC and ADC on RTD Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2022-07-31LFU-372-2 DTS: imx8ulp: Add SCMI sensor nodeYe Li
Add SCMI sensor node and enable pre-relocation for SCMI, so that we can use SCMI thermal driver at early phase of u-boot. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2022-07-29LF-6692-3 imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will panic. We use SIM GPR0 to pass the info from SPL to u-boot, as before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-29LF-6692-2 imx8ulp: Remove the TRDC configure from A35Ye Li
As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-29LF-6692-1 imx8ulp: xrdc: Fix DID0 access DDR in MRC4Ye Li
eDMA1 and USHDC0 access to DDR are controlled by MRC4, so must configure the MRC4 for DID0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2022-07-26LFOPTEE-169 imx8ulp: s400: start the S400 RNG at bootClement Faure
On the imx8ulp A1 SoC, the S400 RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2022-07-26MA-20464 imx8mp: move enet1 to domain 1Ji Luo
move the enet1 to mcu domain as mcu may use it. Change-Id: I65d42d37c97139cf51b00f541e6688e2a97cc624 Signed-off-by: Ji Luo <ji.luo@nxp.com>
2022-07-18LFU-332-8: dts: arm: imx8mm ab2: target board supportAdrian Alonso
Add device tree configs for audio board 2.0 for common imx8mm som modules Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-7: arm: mach imx8m: imx8mm ab2 target board configsAdrian Alonso
Add iMX8M Mini Audio board 2.0 target board configs Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-3: dts: arm: imx8mn ab2: target board supportAdrian Alonso
Add device tree configs for audio board 2.0 for common imx8mn som modules Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-332-2: arm: mach imx8m: imx8mn ab2 target board configsAdrian Alonso
Add iMX8M Nano Audio board 2.0 target board configs Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18MLK-25979-3 imx8ulp: xrdc: Set MRC4/5 for access DDR from A35 and APD PERYe Li
iMX8ULP A1 S400 ROM will remove the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-2 imx8ulp: soc: Limit the eMMC ROM API workaround to A0.1 partYe Li
Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18MLK-25979-1 imx8ulp: soc: Get chip revision from SentinelYe Li
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-18LFU-361-3 arm: dts: imx93: move usb i2c devices to i2c3Clark Wang
According to the board design change, move USB i2c devices to lpi2c3 bus. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-18LFU-361-2 imx9: clock: correct i2c clock rootClark Wang
The root clock used in imx_get_i2cclk() is incorrect. Change it to LPI2C1_CLK_ROOT. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25975 imx93: Update pinctrl header file in DTS and archYe Li
The DTS imx93-pinctrl.h in u-boot is not latest. It uses wrong select input registers offset. So update this file to align with kernel. We also update imx93_pins in arch to add SION for all i2c and i3c SCL/SDA Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25898 ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25965-12 DTS: imx93-11x11-evk: Add nodes for MIPI DSI displayYe Li
Add nodes for MIPI DSI RM67199 panel and adv7535 DSI to HDMI card Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-11 DTS: imx93: Update imx93 DTSi for mediamix nodesYe Li
Sync iMX93 SoC DTSi with kernel for adding and updating nodes in mediamix Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-10 imx9: clock: Add mxs_set_lcdclk API and Frac PLL rateYe Li
Implement the mxs_set_lcdclk to select video PLL frequency according to pixel clock rate and set MEDIA_DISP_PIX_CLK_ROOT accordingly Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25965-9 video: adv7535: Update compatible stringYe Li
Change the compatible string from 7533 to 7535 to align with kernel Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06MLK-25958 arm: dts: imx93: enable DM clock in SPL for i.MX93Alice Guo
Enable DM clock in SPL for i.MX93. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06MLK-25953-4 misc: s400_api: Use new command request definitionsYe Li
Remove legacy command definitions, change to use new ELE_xxx command request. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-3 imx: ahab: Move imx9 and imx8ulp AHAB support togetherYe Li
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since both of them use same sentinel ELE APIs Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-2 imx93: ahab: Get and decode AHAB eventsYe Li
For ahab_status command, support to get and decode AHAB events Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25953-1 s400_api: Add get_events APIYe Li
Add get_events API to retrieve any singular events that has occurred since the FW has started from sentinel Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06MLK-25902-1 gpio: adp5585: update adp5585 gpio driverAlice Guo
The adp5585 used on i.MX93 has 10 GPIOs, so we update ADP5585_MAXGPIO, ADP5585_BANK and ADP5585_BIT. GPIO_x_DIR equals to 0 for input and 1 for output. Make corresponding changes in adp5585_get_function. Initialize plat->dat_out and plat->dir in adp5585_probe. Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFOPTEE-158 imx9: add OPTEE device tree node supportClement Faure
Add the FDT overlay support for OPTEE. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2022-07-06MLK-25904-1 arm: dts: imx93: add a per clock for LPUART1Alice Guo
When CLK is enabled, get_lpuart_clk_rate() needs to get a per clock of lpuart, so that add a per clock for lpuart1. Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-338-2 imx9: ahab: Fix lifecycle and remove debug codesYe Li
Update lifecycle decoding to get lifecycle from FSB LMDA status. Remove unused debug codes Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-337 imx9: Remove DDRMIX slice power cycleYe Li
When A55 boot, DDRMIX is default power on. It is not needed to do additional power off/on cycle to DDRMIX SRC slice. This power cycle was thought to resolve DDR PHY accessing issue, but actually the issue is caused by wrong DDR PLL setting which has been fixed. So remove the unnecessary power cycle. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-49 imx93_evk: Set ARM clock to 1.7GhzYe Li
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC to Overdrive voltage 0.9V Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-48 imx93_evk: Add iMX93 11x11 EVK board supportYe Li
Add board codes and defconfig for i.MX93 11x11 EVK board. Supported functions: UART, USB host/gadget/typc/pd, I2C, DDR, clock, SD/eMMC, eQoS, FEC, GPIO, IO Expander, PMIC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-47 arm: dts: Add iMX93 11x11 EVK supportYe Li
Add DTS file for i.MX93 11x11 EVK board. Support basic functions like: UART, USB, I2C, PMIC, FEC, eQoS, SD, eMMC, Sentinel MU, pinctrl. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-46 arm: dts: Add i.MX93 SoC DTSi fileYe Li
Add the DTSi file and DT header files for i.MX93 SoC Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFU-330-44 arm: imx9: Add i2c clock supportYe Li
Add clock interfaces to init and get lpi2c clock. By default we set lpi2c clock rate to 24Mhz. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-43 arm: imx9: Enable access to flexspi memory mapped spaceYe Li
Add flexspi memory mapped space to MMU table to allow read to flexspi NOR flash Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-07-06LFU-330-42 ddr: imx9: enable Performance monitor counterYe Li
Add Kconfig for enabling reference events counter in DDRC performance monitor by default Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-41 ddr: imx: Add i.MX9 DDR controller driverYe Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-40 arm: imx9: clock: Add DDR clock supportYe Li
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-39 arm: imx9: Support multiple env storages at runtimeYe Li
Select env storages according to boot device at runtime Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-38 imx9: Support booting m33 from AcorePeng Fan
Add bootaux command to support on-demand booting M33 from u-boot. It kicks M33 via ATF by "bootaux 0x201e0000 0" Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-37 arm: imx9: Add M33 release prepare functionYe Li
To support on-demand booting M33 image from A core. SPL needs to follow M33 kick up sequence to release M33 firstly, then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick M33 to run. The prepare function also works around the M33 TCM ECC issue by clean the TCM. Also enable sentinel handshake and WDOG1 clock for M33 stop and reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-36 misc: s400_api: introduce ahab_release_m33_troutPeng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel release M33 trout and make sure M33 could boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-06LFU-330-35 arm: imx9: Add MIX power initYe Li
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation of MIPI DSI/CSI, USBPHY after the power up. SPL should call the power init in its boot sequence before accessing above three MIX and USB. Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-31 arm: imx9: Add gpio registers structureYe Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio driver Signed-off-by: Ye Li <ye.li@nxp.com>
2022-07-06LFU-330-30 arm: imx93: Add SoC level support for USBYe Li
Add SoC level support for USB driver: 1. Add USB clock init 2. Clear USB PHY isolation Signed-off-by: Ye Li <ye.li@nxp.com>
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