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colibri-imx6ull ethernet device is fec2, while the optional secondary
ethernet is fec1, update the ethernet aliases in the .dts file so that
ethaddr is set to fec2 and eth1addr to fec1.
Without this change the ethernet interfaces have a different
mac address between Linux and U-Boot.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
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Add code to build the eMMC variant of the Colibri iMX6ULL, i.e. the
'Colibri iMX6ULL 1GB' which has a eMMC instead of the raw NAND used
on other SKUs.
Related-to: ELB-4056, ELB-4057
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Since NXPs 5.4. release zeros are needed at the end of the bootloader.
Assume that never more than 10k of padding is needed and skip the
shell magic to get a correct size.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
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The recovery image needs to support both Colibri-iMX7 NAND and
Colibri-iMX7 eMMC modules. Forward port the solution for this
from u-boot 2016.11, originally developed by
Stefan Agner <stefan.agner@toradex.com>.
Related-to: TEI-775
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
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OF graph endpoint connections must be bidirectional and dtc warn if they
are not. i.MX7 based DTs have an error and generate
warnings:
arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/replicator/ports/port@0/endpoint: graph connection to node
'/soc/tpiu@30087000/port/endpoint' is not bidirectional
arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/soc/tpiu@30087000/port/endpoint: graph connection to node
'/replicator/ports/port@1/endpoint' is not bidirectional
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
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NAND modules (Colibri Vybrid, iMX7, iMX6ULL) require the images with
1024 prepending bytes.
Add the u-boot-nand.imx target which enables with CONFIG_IMX_NAND
option.
Related-to: TEI-775
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
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imx-bootaux loads an elf file linked for an auxilary core. Thus the
loader function requires address translation from the auxilary core's
address space to where those are mapped into U-Boot's address space.
So the elf loader is specific and must not be replaced with a generic
loader which doesn't provide the address translation functionality.
Fixes commit 805b3cac1e0 ("lib: elf: Move the generic elf
loading/validating functions to lib")
Related-to: ELB-3520
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Rename EEPROM nodes.
Create aliases for EEPROM to unify their order:
eeprom0 - on-module EEPROM
eeprom1 - carrier-board EEPROM
eeprom2 - MIPI-DSI to HDMI adapter EEPROM
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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According to i.MX 7Solo Applications Processor Reference Manual,
2.1.3 Cortex-M4 Memory Map, M4 can address only 1536MB of DDRC
(Start Address: 0x8000_0000; End Address: 0xDFFF_FFFF).
Correct DDRC size to 0x60000000.
Fixes: c0f037f6("mach-imx: bootaux: elf firmware support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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1. Move u-boot specific nodes to u-boot dts include: legacy lcdif
node and aliases.
2. Add iomux configuration for LCD.
3. Drop un-needed u-boot,dm-pre-reloc for alias node.
4. Fix display-timings, use the one from Toradex downstream kernel [1]
[1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n206
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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1. Move aliases and legacy lcdif node to the u-boot specific dts include.
2. Provide proper display timings, as in the downstream Toradex kernel
[1].
[1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n183
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
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currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Replace printf() and debug() by log_err() and log_debug().
"No reserved memory region found in source FDT\n" is not an error but a
debug information.
%s/can not/cannot/ - use the more common spelling.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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fdtdec_get_addr_size_no_parent is not an optimized version if parent
node is already available with the caller.
Use fdtdec_get_addr_size_auto_parent to read the "reg" property
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
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Not all errors are fatal. If a reserved memory node already exists in the
destination device tree, we can continue to boot without failing.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
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SYSRESET uclass driver already provides all the reset APIs, hence
exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the
reserved memory node for PMP protected memory regions. All RISC-V
boards need to copy the reserved memory node from the device tree
provided by the firmware to the device tree used by U-Boot.
Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
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The FDT blob might not have sufficient space to hold a copy of
reserved memory node. Expand it before the copy.
Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
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The copy of reserved memory node from source dtb to destination dtb
can be avoided if they point to the same place. This is useful when
OF_PRIOR_STAGE is used.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
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Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3188 cpu init and APLL fix;
- rk3399: Add BOOTENV_SF command;
- rk3288 correct vop0 vop1 setting;
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Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.
This fixes write to invalid address.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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Since commit:
commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc
Author: Michael Walle <michael@walle.cc>
Date: Thu May 7 00:11:58 2020 +0200
phy: atheros: ar8035: remove static clock config
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
, the clock output setting for the AR803x driver is removed from being
hardcoded in the PHY driver and should be passed via device tree instead.
Update the device tree with the "qca,clk-out-frequency" property so that
Ethernet can work again.
Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
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Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
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Current aliases missed gpio0 node, and this node shoud be
aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we
will get below message when running "gpio status" command, and
see the reason by "dm uclass".
=> gpio status
Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000'
Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000'
Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000'
=> dm uclass
uclass 36: gpio
0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1)
1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0)
2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1)
3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2)
4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3)
5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4)
6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5)
7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot
text base is picked as the one used by various MX7 boards. The SPL
text base however is different.
The SPL text base is set to 0x912000 instead of the usual 0x911000,
that is because the 0x911000 value cannot work. Using 0x911000 as a
SPL text base will result in the DCD header being placed below the
0x911000 address, which is a reserved SRAM area which must not be
used. This will actually trigger eMMC boot failure on MX7D at least.
Hence the increment.
Update all boards affected by this SPL problem to the new SPL_TEXT_BASE.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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There are systems where board_early_init_f() is plain empty. Switch
the config option from "select" to "imply", to permit user to unset
the BOARD_EARLY_INIT_F if it were to be empty.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2ccea9386726d8b9831dfc310589548
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2ccea9386726d8b9831dfc310589548
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the phy-mode accordingly to fix the regression.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- fix SD card cart detect on DHCOM and ST boards
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The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This avoid potential issue for SDCard boot:
the card detect fails with floating gpio.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
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The PSCI nodes are currently not populated for the Tegra210 and Tegra186
devices. This prevents the PSCI driver from being able to identify the
PSCI method used by these devices and causes the probe of the PSCI
driver to fail.
Since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was
added, which moves the PSCI EFI system reset handler into the PSCI
driver, this has prevented the EFI system reset from working for
Tegra210 and Tegra186. Therefore, populating these nodes is necessary
to fix the EFI system reset for Tegra210 and Tegra186.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
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Add OP-TEE firmware node in stm32mp15 U-Boot DTSI. This node is
needed since commit [1] that changed U-Boot/stm32mp15 to detect
OP-TEE availability by probing the resource instead of relying on
U-Boot configuration. The software sequence implemented by [1] is
fine but U-Boot DTS/DTSI files were not updated accordingly since,
hence OP-TEE presence is never detected by U-Boot, preventing Linux
kernel from using OP-TEE resources.
For consistency and to synchronize stm32mp15 DTSI files (excluding
U-Boot specific DTSI files) with the Linux kernel ones, this change
also moves the OP-TEE reserved memory nodes from board generic DTSI
files to U-Boot specific board DTSI files.
Link: [1] commit 43df0a159df6 ("stm32mp1: dynamically detect op-tee presence")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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Fix the sequence in stm32mp1 fdt.c that disables OP-TEE resources
defined in FDT when U-boot detects OP-TEE firmware is not present.
Before this change, helper function stm32_fdt_disable_optee()
set property status to "disabled" for the OP-TEE reserved memory
nodes but this has no impact since Linux kernel does not consider
the status property for reserved-memory subnodes. This change
make U-Boot to attempt to delete the node instead.
Fixes: 4a1b975dac02 ("board: stm32mp1: reserve memory for OP-TEE in device tree")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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- fsl_esdhc sdr104 and hs200 fix and error path fix
- fsl_esdhc workaround 3.3v io issue
- ca_dw_mmc cleanup
- presidio-asic emmc DT update.
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Change DT compatibility name to match change in driver's name.
Remove unused io_ds and fifo_mode fields from DT.
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Tom Rini <trini@konsulko.com>
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- cyclone5 bugfix
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Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.
After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.
Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)
After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.
Remove it.
Acked-by: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.
Remove it.
Acked-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.07
-----------------
- mx53: mx53menlo Convert to DM_ETH, fix fail boot
- imx8mp_evk: fix boot issue
- MX6, display5: fix environment
- drop warnings (watchdog) for i.MX8mm i.mx8mp
- enable bootaux for i.MX8M
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
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This reverts commit 1f63ee656698724bcdc4e711b4ccd267f6bf64ab.
As reported by Ye Li on ML:
1. Removing the image_offset will break secondary (redundant) boot support for sd and emmc.
2. When booting from emmc boot partition, the image_offset is 0. But the flash.bin
generated by mkimage with imximage-8mp-lpddr4.cfg is for sd. It expects to be burn at 32KB offset.
The fit offset 0x60000 has already included the 32KB offset. So when you burn this flash.bin
to emmc boot partition at offset 0, the fit offset should subtract the 32KB (0x60000 - 0x8000).
Signed-off-by: Stefano Babic <sbabic@denx.de>
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- DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug
fixes
- Add TBI PHY access through MII
- DDR: Rework errata workaround for A008109, A008378, 009942
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Convert the board to DM_ETH instead of legacy networking. This requires
a minor addition to the DT to satisfy the requirement for specifying a
PHY node. No functional change from board user perspective.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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