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2017-09-14ARM: at91: spl: Add macro CONFIG_XXXX_BOOT supportWenyou Yang
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of the CONFIG_SYS_USE_XXXX option, which is declared by CONFIG_SYS_EXTRA_OPTIONS option. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Remove hardware.h included in configsWenyou Yang
As said in READRE.kconfig, include/configs/*.h will be removed after all options are switched to Kconfig. As the first step, remove the follow line from include/configs/*.h. #include <asm/hardware.h> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Add the SoC options to KconfigWenyou Yang
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3 and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is deprecated, add the SoC options to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Move CONFIG_AT91FAMILY option to KconfigWenyou Yang
Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header file to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14board: atmel: Add SAMA5D27 SOM1 EK boardWenyou Yang
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package. The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: Get the Chip ID of SAMA5D2 SiPWenyou Yang
The SAMA5D2 SiP(System in Package) has different Chip IDs in the CHIPID and CHIP_EXID registers. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: mach: Add missing defines of MPDDRCWenyou Yang
Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Add boot device for boot from QSPIWenyou Yang
Add the boot device for booting from the QSPI flash. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Add mck function to lower rate while switchingWenyou Yang
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happens on SAMA5D2 as exitting from the ROM code. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Adjust switching to oscillator for SAMA5D2Wenyou Yang
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its freqency is valid. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14atmel: common: Add function to display via DM_VIDEO's APIWenyou Yang
Add a function to display the company's logo and board information via the API from DM_VIDEO. This function can be shared by other atmel boards, so locate it in board/atmel/common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: dts: at91: sama5: Add the sfr nodeWenyou Yang
For sama5d2, add the sfr node with syscon support. In order to access the SFR_UTMICKTRIM register for the utmi clock driver, add the phandle property for the utmi node to point to the sfr node. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14clk: at91: utmi: Set the reference clock frequencyWenyou Yang
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-13Convert CONFIG_EMIF4 et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_EMIF4 CONFIG_SDRC Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-13arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5Adam Ford
The DTS files had some spacing issues and they needed fixing. This pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5. To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. Signed-off-by: Adam Ford <aford173@gmail.com> V3: The resync broke card detect on MMC1 on Logic PD's Torpedo, so we add the cd-invert to the Torpedo's -u-boot.dtsi file. V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo Remove the need for the second patch in the series
2017-09-13ARM: dts: ethernut5: Fix the build warningWenyou Yang
Fix the building warning as below: ---8<---- Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50 Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50 --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-12ARM: DRA72x: Add support for detection of DRA71x SR 2.1Vishal Mahaveer
DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-12dma: import linux/dma-direction.h to consolidate enum dma_data_directionMasahiro Yamada
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete duplicated definitions of enum dma_data_direction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-09-12armv8: mmu: add space around operatorAndy Yan
Add space around operator "+", make it match the coding style. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12armv8: mmu: remove unused macro definitionAndy Yan
Macro VA_BITS and PTE_BLOCK_BITS are not used in the code, so remove them. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-09-12Merge git://git.denx.de/u-boot-dmTom Rini
2017-09-11dm: test: replace dm_scan_dt() by of dm_extended_scan_fdt() in dm_do_testPatrice Chotard
This allows to scan the DT including all "clocks" node's sub-nodes in which fixed-clock are defined. All fixed-clock should be defined inside a clocks node which collect all external oscillators. Until now, all clocks sub-nodes can't be binded except if the "simple-bus" compatible string is added which is a hack. Update test.dts by moving clk_fixed node inside clocks. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11dm: core: Add ofnode_for_each_subnode()Simon Glass
Add a convenience macro to iterate over subnodes of a node. Make use of this where appropriate in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-09-11sandbox: Convert SANDBOX_BITS_PER_LONG to KconfigBin Meng
Convert SANDBOX_BITS_PER_LONG to Kconfig and assign it a correct number depending on which host we are going to build and run. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11sandbox: Introduce Kconfig option for 32/64 bit hostBin Meng
It seems most of the time we are building and running sandbox on 64-bit host. But we do support 32-bit host as well. Introduce Kconfig option for this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11board: sama5d4_xplained: Set mac address from eepromWenyou Yang
Add the code to set the ethernet mac address from eeprom by using the common code from the common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11board: sama5d2_xplained: Replace code to set mac addressWenyou Yang
Replace the code to set the ethernet mac address with the code from the common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11board: atmel: Create board/$(VENDOR)/common folderWenyou Yang
Create board/$(VENDOR)/common folder to accommodate the common code shared by other atmel boards, now put the code to set ethernet mac address from eeprom, which uses the i2c eeprom driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-11board: ti: am57xx: Add dt support for BeagleBoard-X15 revCLokesh Vutla
Add support for selecting proper dtb for am57xx BeagleBoard X15 revC u-boot from FIT Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11board: ti: am571x: Add 666MHz support for AM571x IDKSteve Kipisz
AM571x supports DDR running at 666MHz. Right now it is clocked at 532MHz which is lower than what is supported. In order to have maximum performance on AM571-IDK, switch DDR to 666MHz. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11board: ti: dra76: Add dt supportLokesh Vutla
Add support for selecting proper dtb for dra76x u-boot from FIT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11arm: dts: Add u-boot specific compatiblesLokesh Vutla
Separate out u-boot specific compatibles from dts files. This will help in syncing dts files in future. Also these will get deleted eventually once respective drivers are capable of handling Linux dts files. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11arm: dts: dra7: sync DT with latest LinuxLokesh Vutla
Sync all dra7* specific dts files with the upstream kernel including changes queued for 4.14 https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v4.14/dt-v3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11board: ti: dra76-evm: Add DDR dataLokesh Vutla
dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11board: ti: dra76-evm: Add the pmic dataKeerthy
dra76-evm uses lp8736 and tps65917 pmic for powering on various peripherals. Add data for these pmics and register for dra76-evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11arm: dra76: Add support for ES1.0 detectionPraneeth Bajjuri
dra76 family is a high-performance, infotainment application device, based on OMAP architecture on a 28-nm technology. This contains most of the subsystems, peripherals that are available on dra74, dra72 family. This SoC mainly features Subsystems: - 2 x Cortex-A15 with max speed of 1.8GHz - 2 X DSP - 2 X Cortex-M4 IPU - ISS - CAL - DSS - VPE - VIP Connectivity peripherals: - 1 USB3.0 and 3 USB2.0 subsystems - 1 x SATA - 2 x PCI Express Gen2 - 3-port Gigabit ethernet switch - 2 x CAN - MCAN Adding CPU detection support for the dra76 ES1.0 soc and update prcm, control module, dplls data. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11arm: dra7: Kconfig: Select LP87565 related configsLokesh Vutla
LP87565 is present on dra76-evm. Select it for TARGET_DRA7XX_EVM. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-11palmas: Add support for powering different ldosLokesh Vutla
It is not necessary that ldo1 is used to power on mmc. So, add support for passing ldo registers for powering on mmc. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11arm: omap5+: Add board specific ldo poweringLokesh Vutla
It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-11armv8: fsl-layerscape: Add back L3 flushing for all exception levelsYork Sun
CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11armv8: ls1088a: add PCIe dts nodeHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: ls1088a: fix the MMU table for pcie config spaceHou Zhiqiang
The pcie config space of ls1088a is different from ls2080a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl-layerscape: Fix MC reserved memory calculationYork Sun
In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-11armv7: Add workaround for USB erratum A-009007Ran Wang
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv7: Add workaround for USB erratum A-008997Ran Wang
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv7: Add workaround for USB erratum A-009798Ran Wang
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv7: Add workaround for USB erratum A-009008Ran Wang
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-009007Ran Wang
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-008997Ran Wang
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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