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2019-06-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu
Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: fix config dependency for layerscape pci codeAlex Marginean
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Change bootcmd update logicPankit Garg
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Update qspi clk cfgPankit Garg
Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19ARM: dts: ls1021a: Fixed reg for sata nodePeng Ma
This patch is to fixed the reg read to "0" for armv7 architecture. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8/fsl-layerscape: Add loop to check L3 dcache statusMeenakshi Aggarwal
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable eSDHC controllersYinbo Zhu
This patch is to enable esdhc controllers for lx2160aqds Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add ecc address node for sata.Peng Ma
Move the ecc addr from driver to dts Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch3: add clock support for the second eSDHCYangbo Lu
Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable sataPeng Ma
Change sata node status to enable sata. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add other serdes protocal supportXiaowei Bao
Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB errarum A-009007Yinbo Zhu
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB erratum A-008997Ran Wang
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-17Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Drop zipitz2 board (Tom) - Add DEPRECATED option (Tom) - Mark legacy or non-dm drivers as DEPRECATED (Jagan)
2019-06-15Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- SPL size check for Gen5, i2c enablement for S10
2019-06-14sh: r0p7734: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14sh: ap325rxa: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14sh: ap_sh4a_4a: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14sh: ms7750se: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14sh: ms7722: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14sh: espt_giga: Remove the boardMarek Vasut
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-06-14arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-14arm: dts: Stratix10: Enable i2cLey Foon Tan
Enable i2c1 in Stratix 10 devkit. SOCFPGA_STRATIX10 # i2c bus Bus 0: i2c@ffc02900 SOCFPGA_STRATIX10 # i2c dev 0 Setting bus to 0 SOCFPGA_STRATIX10 # i2c probe Valid chip addresses: 14 4C 51 68 74 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-06-13Kconfig: Add SPI / SPI_FLASH as dependenciesTom Rini
In order to use CMD_SF / CMD_SPI / ENV_IS_IN_SPI_FLASH we need to have the SPI (or SPI_FLASH/DM_SPI_FLASH, for CMD_SF) enabled. Express this in the Kconfigs. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-13arm: Remove zipitz2 boardTom Rini
Per discussion on the list, drop this board again. Cc: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-11Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini
- Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imxTom Rini
u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
2019-06-11arm: dts: imx6qdl-u-boot: Alias usb0 to usbotgSjoerd Simons
All i.mx6 boards seems to have moved to DM_USB, however gadget support for mx6 is still pre-DM as CI_UDC isn't converted yet. To make this work the usb otg controller used for gadgets needs to be usb number 0. Add an alias for this directly in the main u-boot mx6qdl dtsi so it doesn't need to be done for each board separately. This fixes regressions wrt. usb gadget functionality in several boards that have gadget functions enabled in their config, but no usb0 alias in their device-tree. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-06-11imx: define ARCH_MXC for i.MX8/8M/7ULPPeng Fan
Without this definition, fsl_esdhc will access reserved registers on i.MX chips, so define ARCH_MXC to fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11imx: drop imx-regs.hPeng Fan
imx-regs.h under arch-imx has no user, drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-11imx8: cpu: get temperature when print cpu descPeng Fan
Read the temperature when print cpu inforation. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-06-11ARM: imx: vining2000: Convert MMC and block to DMMarek Vasut
Enable DM block and DM MMC support on iMX6SX VINING|2000 . Convert board code to match the DM support. This disables USB mass storage support due to missing DM USB, however that will be re-enabled in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: dts: imx: vining2000: Import VINING|2000 DT from LinuxMarek Vasut
Import iMX6SX VINING|2000 device tree from Linux 5.1.1 b724e9356404 . Enable DT control in full U-Boot . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: imx: Rename VINING|2000Marek Vasut
The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-11ARM: imx: Call imx_pcie_remove() only for non-DM PCI driverMarek Vasut
The DM iMX PCI driver has DM_FLAG_OS_PREPARE set and will call imx_pcie_remove() from the .remove callback. Do not call it from the architecture code again. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11imx: Extend PCL063 support for phyCORE-i.MX6ULL SOMParthiban Nallathambi
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM. CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg) Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-06-11board: toradex: add apalis imx8qm 4gb wb it v1.0b module supportMarcel Ziswiler
This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module. Unlike the V1.0A early access samples exclusively booting from SD card, they are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports either booting from the on-module eMMC or may be used for recovery purpose using the universal update utility (uuu) aka mfgtools 3.0. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Gigabit Ethernet - GPIOs - I2C Unfortunately, there is no USB functionality for the i.MX 8QM as of yet. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11imx8qm: fix cpu frequency reportingMarcel Ziswiler
CPU frequency reporting failed with the following error message being printed: sc_pm_get_clock_rate: resource:507 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QM RevB A53 at 0 MHz Fix this by differentiating between the A35 as found on the i.MX 8QXP and the A53 as found on the i.MX 8QM SoCs. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4Marcel Ziswiler
Add support for i2c0, i2c1, i2c2, i2c3 and i2c4. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4Marcel Ziswiler
Add support for lpuart1, lpuart2, lpuart3 and lpuart4. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11ARM: imx: novena: Convert block devices to DMMarek Vasut
Enable DM block, DM MMC and DM SATA support on iMX6Q Novena convert board code to match the DM support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Vagrant Cascadian <vagrant@debian.org>
2019-06-11ARM: dts: imx: novena: Import Novena DT from LinuxMarek Vasut
Import iMX6Q Novena device tree from Linux 5.1-rc7 37624b58542f . Enable DT control in full U-Boot . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Vagrant Cascadian <vagrant@debian.org>
2019-06-11pico-imx7d: Correct uart clock rootJun Nie
Correct uart clock root ID. Incorrect ID may result the clock is gated because rate value 0 is returned in imx_get_uartclk() The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled because init_clk_uart() will enable all uart clocks in that case. Signed-off-by: Jun Nie <jun.nie@linaro.org>
2019-06-11imx: mx7: Skip secure init in arch_cpu_initJun Nie
Skip secure related initialization in arch_cpu_init if low level init is skipped. Because these should be done in early stage firmware, such as ARM trusted firmware. Signed-off-by: Jun Nie <jun.nie@linaro.org>
2019-06-11arm, imx, Makefile: fix u-boot-dtb.imx build in CONFIG_MULTI_DTB_FIT caseHeiko Schocher
in case CONFIG_MULTI_DTB_FIT is set and u-boot-dtb.imx image is build, currently u-boot-dtb.bin is used for generating the u-boot-dtb.imx binary, which is wrong, as it contains only a dtb blob not the fit.blob Use instead the u-boot-fit-dtb.bin for generating u-boot-dtb.imx which contains the fit.blob. Signed-off-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-28 01:24:23 +0000