summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2011-11-15arm: Tegra: make some header files common for Tegra3 LCD useTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=built Seaboard and Waluigi AOK Change-Id: Ia860abf5ef3af66b3a39d4c57192455986b7a4f4 Reviewed-on: https://gerrit.chromium.org/gerrit/11704 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-15tegra: spi: add SFLASH and SLINK driversChe-Liang Chiou
BUG=chromium-os:21033 TEST=run `sf erase, write` and then `sf read` on seaboard verify the data it reads from SPI flash matches that it writes to Change-Id: I1b04afa4b54738cd93be29b70f428bdc3e6b234f Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/11472 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15spi: add TEGRA_SLINK4_BASE and TEGRA_SPIFLASH_BASE in prep for tegra3Che-Liang Chiou
BUG=chromium-os:21033 TEST=emerge-{tegra2_seaboard,waluigi} chromeos-u-boot Change-Id: Icee2c26f36937e96c24318979179ba3a0cbfc09c Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11597
2011-11-15arm: Tegra: power: make power.c/.h common for future Tegra3 LCD useTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=built Seaboard and Waluigi OK. Booted Waluigi OK. Change-Id: I1bfbe03945d7dae44e0840349b9698fc08cef07d Reviewed-on: https://gerrit.chromium.org/gerrit/11504 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-15arm: Tegra: add new clocks for T30 LCDTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com> BUG=none TEST=build Seaboard and Waluigi AOK Change-Id: Id8e7227de7898bb9d117bf8d0f293ee5da7dc501 Reviewed-on: https://gerrit.chromium.org/gerrit/11506 Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
2011-11-14arm: tegra2: change initial CPU clock to 312MhzYen Lin
Set CPU clock initially to 312Mhz; once CPU voltage is raised, CPU clock will then be raied to 1.2GHz (for T25) or 1.0GHz (for T20). BUG=chrome-os-partner:5914 TEST=Build and test on Seaboard Change-Id: I0c95a1df6b87c896daca8c03c9dc33b245764621 Reviewed-on: https://gerrit.chromium.org/gerrit/11199 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Doug Anderson <dianders@chromium.org>
2011-11-13spi: rename tegra2_spi to tegra_spi in prep for tegra3Che-Liang Chiou
BUG=chromium-os:21033 TEST=build seaboard successfully Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811 Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/11471 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-03Clean up MTRR 7 right before jumping to the kernelStefan Reinauer
This cleans up the rom caching optimization implemented in coreboot (and needed throughout u-boot runtime. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:6585 TEST=boot coreboot on stumpy Change-Id: I7242c9c2b0546c633be8fb8ebc815ed6e6fda4d1 Reviewed-on: https://gerrit.chromium.org/gerrit/11138 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-28mmc: tegra3: Add MMC support for Tegra3 (specifically, waluigi)Doug Anderson
BUG=chromium-os:21540 TEST=Able to talk to MMC1 on Waluigi w/ future config changes. Specifically: 1. mmcinfo 0 - works (shows info) 2. mmcinfo 1 - works (shows info) 3. mmc rescan 1; mmc part 1 - works (shows partitions) Change-Id: I730d3b91088f20ccf7ca20f3f31f7d59514af243 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/10661 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-27Use new VBNV section in coreboot tableStefan Reinauer
... rather than parsing the coreboot option table BUG=none TEST=boot tested on Stumpy Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I0814dd6c37cf826fda55a0f4acd6a1763b0626db Reviewed-on: https://gerrit.chromium.org/gerrit/10758 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-25pmu: Move pmu.c exported function defs to non-arch pmu.hDoug Anderson
Previously the exported function definitions for pmu.c were split among board.h, emc.c, and the architecture specific pmu.h. Create a non-architecture-specific pmu.h and put them there. NOTE: The arch/pmu.h file should probably be removed eventually in favor of the device tree, since it really just defines how a particular PMU is used by a particular family of board. BUG=chromium-os:21540 TEST=Compiled for seaboard Change-Id: Ia026e3ff3f1f465be629cc8a348879d2d1564686 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10456 Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-10-25pmu: Move definition of abs() and stp() out of pmu header fileDoug Anderson
These two functions were only used in pmu.c, so there was no reason for them to be in the header file. They probably should be moved elsewhere eventually, but this is a better location than they were. BUG=None TEST=Compiled Change-Id: Ia13cfd0fd828589862bfd555c3a34d3b6b4bda1c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10455 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com>
2011-10-20Import the glibc implementation of x86 memset into u-bootGabe Black
I ran four iterations with the two implementations and used Vadim's CBMEM infrastructure to measure the time they took. These are all in microseconds, and the timestamp portion of the raw output of cbmem.py is included in the bug. The new implementation is about twice as fast as the old. Old: 1. 418,286 2. 418,302 3. 418,298 4. 418,290 New: 1. 184,800 2. 194,629 3. 194,188 4. 192,718 BUG=chrome-os-partner:6487 TEST=Booted on Stumpy. Change-Id: Iba398929cbba395e10851d676ae9d356ae670f41 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10284 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-20tegra3: Add T30 supportSimon Glass
This adds support for T30 init to ap20.c, and modifies the board file to cope with it also. The only thing missing at this point is the pinmux setup. BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: I3e75245c1fdb99bc15eadcf60b173e6f0d9bb56c Reviewed-on: http://gerrit.chromium.org/gerrit/8704 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-13Reorder x86's post relocation memory layoutGabe Black
This changes the layout in decreasing addresses from: 1. Stack 2. Sections in the image 3. Heap to 1. Sections in the image 2. Heap 3. Stack This allows the stack to grow significantly more since it isn't constrained by the other u-boot areas. More importantly, the generic memory wipe code assumes that the stack is the lowest addressed area used by the main part of u-boot. In the original layout, that means that u-boot tramples all over itself. In the new layout, it works. BUG=chrome-os-partner:6194 BUG=chrome-os-partner:6195 TEST=Booted on Stumpy. Change-Id: I0484ad37ba15f63cb0fb289118cad360817ad11f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10006 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-10-13Fill in the dram info using the e820 map on coreboot/x86Gabe Black
This way when that dram "banks" are displayed, there's some useful information there. The number of "banks" we claim to have needs to be adjusted so that it covers the number of RAM e820 regions we expect to have/care about. This needs to be done after "RAM" initialization even though we always run from RAM. The bd pointer in the global data structure doesn't automatically point to anything, and it isn't set up until "RAM" is available since, I assume, it would take too much space in the very constrained pre-RAM environment. BUG=None TEST=Booted on Stumpy and saw reasonable contents in the "DRAM Configuration" portion of the serial output. Change-Id: Iced6c6717ba8464b972293c99505735df1a244c3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10010 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-12Add a CBMEM timestamp generated right before the kernel startup.Vadim Bendebury
To maintain the initialization state of the timestamp facility, the pointer to the CBMEM section containing the timestamp table should be kept in the .data section (so that it is maintained across u-boot relocation). BUG=chromium-os:20733 TEST=manual . build a new firmware image . program it on a Stumpy configured for ssh communications . reboot the stumpy . examine the timestamp log (host) ssh <target ip addr> /var/cbmem.py| grep -A1 'time base' time base 2195144, total entries 4 1:77,700 2:767,214 1000:1,409,204 1100:2,274,851 observe the new timestamp entry added to the log. Change-Id: I71edb31f1c0c7b3d24dcc9a611efc999615e09d2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/10003 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-11tegra: Correct GPIO definitions for Tegra2Simon Glass
The GPIO definitions for Tegra2 were incorrectly matched up with Tegra2. The layout is actually different, so GPIOs beyond port D do not work. This separates out the GPIO headers again, so that Tegra2 and Tegra3 have separate structure definitions. BUG=None TEST='vboot_test gpio' on Kaen; see that it responds to google rec, power, lid correctly Change-Id: I8540a87c8faa7179c8f0d44ef3f18b3c576392cc Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/9847 Reviewed-by: Bryan Freed <bfreed@chromium.org> Tested-by: Bryan Freed <bfreed@chromium.org>
2011-10-07Fix the inline assembly constraints in boot_zimageGabe Black
It's possible that the compiler will decide to put the kernel entry point into register %ebp which the assembly blob will set to 0 manually before it's used. These new constraints will force it to use %eax for the kernel entry point, and also tell it that the %ebp register is modified. BUG=None TEST=Built and booted on Stumpy and verified that the crash entering the kernel no longer happens. Change-Id: Iae321543e610f2084957978e438e91b1081dbc89 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/9764 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2011-10-07arm: tegra3: Add pinmux functionsJimmy Zhang
The pinmux functions for Tegra3 are quite different from Tegra2, since we can adjust the setting for each individual pin. We try to keep the same top-level interface where possible. (sjg@chromium.org tidied up for 80cols) BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: I5bb109e73dc69c3424fe71978417b3f2b210a540 Reviewed-on: http://gerrit.chromium.org/gerrit/8692 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-07tegra3: i2c: Add low level functions for T30Simon Glass
We need these functions to set up the power chip during low-level init. BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: I69b9d3c12581e0a71db39b031b9ea2ef4ec184bf Reviewed-on: http://gerrit.chromium.org/gerrit/8696 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-07tegra3: Add GPIO headerSimon Glass
This header supplies the necessary T30 parts for GPIO access. Since the Tegra3 just adds new fields and they will use the same driver, we move the structure into the common header. BUG=chromium-os:21033 TEST=build and boot on seaboard Change-Id: I3ebf128358d118fc43469ffff839af5027bc6472 Reviewed-on: http://gerrit.chromium.org/gerrit/8693 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-06tegra3: Add new clock definitionsSimon Glass
Tegra3 has a number of additional registers in the clock/reset controller. BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: I34b0e66b2843fd2c2d4ab29fa1b4247b5ead7abf Reviewed-on: http://gerrit.chromium.org/gerrit/8697 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-06tegra3: Add flow controller definitionsSimon Glass
Change-Id: If944692337a24b1720b07460d1490b8cd15e7ef9 Reviewed-on: http://gerrit.chromium.org/gerrit/8703 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-06tegra3: Detect amount of DRAM correctlySimon Glass
Rather than hard-code this, we find out the amount of DRAM we have using the official function. BUG=chromium-os:21033 TEST=build and boot on Seaboard Change-Id: Ibb20f1babc149457857292336ac588cf97fe35fa Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8702
2011-10-06tegra: Move architecture init code into commonSimon Glass
We will want arch_cpu_init() for both T20 and T30, so move it into the common area. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I5d3a1d59da9f8f2300ddce46469fe55caf27b482 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8691
2011-10-06tegra: Remove obsolete commentSimon Glass
This comment is no longer needed BUG=chromium-os:19004 TEST=build and boot on Seaboard Change-Id: Icd2f92f293551173b134d300c8443a6efac63405 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8690
2011-10-06tegra: Add support for 408MHz PLLPSimon Glass
The 216MHz PLLP is not always wanted - this adds support for 408MHz which will be used on T30. BUG=chromium-os:19004 TEST=build and boot on Seaboard Change-Id: I4c053b5a9db4efb7b926ad2c9072f392d24033c9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8689 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
2011-10-06tegra: Detect the number of CPUsSimon Glass
This adds ap20_get_num_cpus() which returns the number of CPUs in the system, and adjusts a clock function to use it. BUG=chromium-os:19004 TEST=build and boot on Seaboard Change-Id: If7b56a2cecfb3d856308cac43dfcb32d3f1fef14 Reviewed-on: http://gerrit.chromium.org/gerrit/8688 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-06Move Starting kernel... message to the function that starts the kernelStefan Reinauer
Because with vboot the message would not be printed otherwise. BUG=none TEST=vboot on a Stumpy, see message about starting the kernel appear. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I73a5230edcc56b1f80acba1b99691cde7fdc33c6 Reviewed-on: http://gerrit.chromium.org/gerrit/8921 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com>
2011-10-05CHROMIUM: Fix gcc 4.6.0 warning if CONFIG_GENERIC_MMC not defined.Doug Anderson
Warning was: board.c: In function 'board_init_r': board.c:514:8: error: variable 'bd' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors The "fix" is to just use the "bd" shortcut in more places. BUG=None TEST=Compiled with waluigi patches (pull from http://gerrit.chromium.org/gerrit/8705) w/ no warnings. TEST=Compiled / booted legacy firmware for Kaen to u-boot prompt. Change-Id: I73d690650b5a09bc456f502ea4b3612b41c78f37 Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8750
2011-10-04tegra: Build early code for ARMv4TSimon Glass
The Tegra family has an ARMv4T chip which runs board_init_f(). It does not support the BLX instruction which the init_sequence function table generates. The easiest fix is to build this file for ARMv4T on Tegra. The alternative is to move the arch_cpu_init() call out of the init sequence. But that fix would not make the reason for the change so obvious. There is no code size impact. BUG=chromium-os:19353 TEST=build and boot on Seaboard Change-Id: Idb0ab17bd0839c472cda7bf4940522245792e328 Reviewed-on: http://gerrit.chromium.org/gerrit/8684 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Don't use board pointer before it is set upSimon Glass
In board_init_f() the gd->bd pointer is not valid when dram_init() is called. This only avoid dying because DRAM is at zero. The common ARM routine sets up the banks in the same way anyway, so we can just remove this code. BUG=chromium-os:19353 TEST=build and boot on Seaboard Change-Id: I81660e67d265031a73b416beaba64ba5a9cbc99d Reviewed-on: http://gerrit.chromium.org/gerrit/8681 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Move common gpio code into arch-tegraSimon Glass
Much of the GPIO header is common between T20 and T30, so move it into a common file to avoid duplication. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: Id8ca0bad87f8b5b27f00acf31081a52d88f1d824 Reviewed-on: http://gerrit.chromium.org/gerrit/8679 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make i2c driver commonSimon Glass
The T20 and T30 i2c peripherals can use the same driver. This renames the driver and puts the header file into the common arch-tegra directory. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: Iec76bb27340db037fdc67b3509fd35f7b5aaeb34 Reviewed-on: http://gerrit.chromium.org/gerrit/8643 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make flow.h commonSimon Glass
The flow controller exists in both T20 and T30, so move it into the tegra-common directory. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: If6b7fea7dc3969139dfeadcf856b8d43d7eb875a Reviewed-on: http://gerrit.chromium.org/gerrit/8642 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make warmboot.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I896719336126346c540bbae0c0559302189460ef Reviewed-on: http://gerrit.chromium.org/gerrit/8641 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make uart.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I71d2cb747d97d8bd4d6c8c03037bb94614a6017f Reviewed-on: http://gerrit.chromium.org/gerrit/8640 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04console: Implement pre-console bufferGraeme Russ
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped. Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Change-Id: I3c4caad276b9e981ebea0a0fb79d85ee3a3bcb7d Reviewed-on: http://gerrit.chromium.org/gerrit/8686 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04console: Squelch pre-console output in console functionsGraeme Russ
There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Change-Id: If62863017eaa48915b721675a5d520f9caa7e5e0 Reviewed-on: http://gerrit.chromium.org/gerrit/8685 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make scu.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I27113943da1e2dd3045f139938bc0c45998a0170 Reviewed-on: http://gerrit.chromium.org/gerrit/8639 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make pmc.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I89c132f9d857a76ee03f24ec910619df00a6d4ac Reviewed-on: http://gerrit.chromium.org/gerrit/8638 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make clk_rst.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: Idc12f106caaaf7601de8e66d8440840375eb9c42 Reviewed-on: http://gerrit.chromium.org/gerrit/8637 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04tegra: Make bitfield.h a common fileSimon Glass
This is needed by both T2x and T3x. BUG=chromium-os:19004 TEST=build and boot on seaboard Change-Id: I03cb8e7b189cae0efb58d1ceed55a1e0dcd57c7f Reviewed-on: http://gerrit.chromium.org/gerrit/8636 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-03Process all cbmem table references consistently.Vadim Bendebury
A few CBMEM table entries are included in coreboot to let u-boot discover the locations of those entries. They all are passed using the same structure within coreboot table. This patch makes use of that structure for all communicated entries (timestam, console and MRC cache). It does not make sense to keep types of pointers in the sysinfo table, as nobody but the respective users of those fields use the types. Let's keep the pointers as void *, this also allows to reduce the amount of include files in systinfo.h and hide the timestamp structures in timestamp.c. BUG=chrome-os-partner:4200 TEST=manual . build the new firmware and program it on a stumpy . restart the machine . after it comes up to ChromeOS, run the cbmem.py utility Observe that timstamp values are displayed, and there is an entry with index 1000 (added by u-boot to the coreboot timestamp table). Change-Id: Icb808145c4c62cee939eceb3d5bf5afb3bcd00d9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8711 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-09-28Track whether u-boot was warm or cold booted, and implement is_processor_resetGabe Black
Code which determined whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point) was partially implemented, and the result was simply dropped when leaving the assembly part of initialization. This change completes the implementation, plumbs the result through to the global data structure, and implements is_processor_reset to check the value there. BUG=chrome-os-partner:5252 TEST=Built and did a twostop boot on Alex. The firmware was resigned using the command below so that the RW firmware would be used. When is_processor_reset was hardcoded to return true all the time, u-boot would go into recovery mode. Now it boots successfully. /resign_firmwarefd.sh image.bin /tmp/image_new.bin ../../tests/devkeys/firmware_data_key.vbprivk ../../tests/devkeys/firmware.keyblock ../../tests/devkeys/firmware_data_key.vbprivk ../../tests/devkeys/firmware.keyblock ../../tests/devkeys/kernel_subkey.vbpubk 1 0 Change-Id: I22b8ed3c3b472807832f1f7e7724f27a218cf4cf Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/8396 Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-09-27Fix global data offset macros which are used in assemblyGabe Black
global_data.h defines a number of offset constants which are used by assembly to access the global data structure. These were partially correct but out of date. This change corrects them. BUG=None TEST=Built and booted twostop on Alex. Change-Id: I0989ee7dae0ef095af54b6df9137e925da3e74a6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/8395 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-09-26Enable coreboot timestamp facility support in u-boot.Vadim Bendebury
This change turns on the code which allows u-boot to add timestamps to the timestamp table created by coreboot. Since u-boot does not use the tsc_t like structure to represent HW counter readings, this structure is being replaced by 64 bit integer. The timestamp_init() function is now initializing the base timer value used by u-boot to calculate the HW counter increments. Timestamp facility is initialized as soon as the timestamp table pointer is found in the coreboot table. The u-boot generated timer events' ID will start at 1000 to clearly separate u-boot events from coreboot events in the timer trace. BUG=chromium-os:20733 TEST=manual A Python script was used to retrieve the CBMEM timestamp table while running CromeOS. The script will later be submitted into the ChromeOS tools directory. The following output was generated by the script: localhost ~ # /var/vbendeb/cbmem.py id 1, value 804,824,023 id 2, value 7,846,816,530 id 1000, value 19,356,528,758 Change-Id: I48c46e7b5cd2b2601d12465e0d8946152f31126e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8274 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-09-24Refactor hw timer code to accommodate execution tracing.Vadim Bendebury
This CL separates the HW timestamp acquisition into an inline function and provides interface to set the base time (to be retrieved from coreboot table). BUG=chromium-os:20733 TEST=manual . build the new firmaware image . bring up a stumpy with the new image to ChromeOS . examine crossystem reported timer values. Observe that the values start with zero and increase monotonously. Change-Id: I4ede0a55112e061e9d3790f01c8ca41a8539364b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8215 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-09-24Retrieve timestamp table information from coreboot table.Vadim Bendebury
This change adds code to process the timestamp table infiormation in case it is included in the coreboot table. coreboot/timestamp.h had to be modified to make it possible to compile in u-boot environment. The upcoming change will modify the timestamp handling code borrowed from coreboot under http://gerrit.chromium.org/gerrit/8164. BUG=chromium-os:20733 TEST=manual . brought up a stumpy to ChromeOS login screen. Change-Id: I008b5e4c971cbb13de2f055f53da6384035df5eb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8222 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Gabe Black <gabeblack@chromium.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-04 22:17:37 +0000