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2020-04-04x86: acpi: Describe USB 3 host controller found on Intel TangierAndy Shevchenko
USB 3 host controller may be described in ACPI to allow users alter the properties or other features. Describe it for Intel Tangier SoC. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-04x86: acpi: Add I²C timings to Intel Merrifield platformAndy Shevchenko
There is established way to provide I²C timings, or actually counters, to the OS via ACPI. Fill them for Intel Merrifield platform. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-04x86: acpi: Refactor XSDT handling in acpi_add_table()Andy Shevchenko
There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: apl: Use cpu_x86_get_count() for cpu_ops.get_countWolfgang Wallner
Use cpu_x86_get_count() to read the number of cores. cpu_x86_get_count() reads the number of CPUs from the device tree. Using this function we can support multiple Apollo Lake variants, e.g.: E3940 (4 cores) and E3930 (2 cores). This was tested on the E3940 and E3930 Apollo Lake variants. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: cpu_x86: Make cpu_x86_get_count() non-staticWolfgang Wallner
The function cpu_x86_get_count() is also useful for other modules. Make it non-static and add a prototype + description. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: p2sb: Drop 'apl' prefixWolfgang Wallner
Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05Revert "x86: use invd instead of wbinvd in real mode start code"Andy Shevchenko
This reverts commit 0d67fac29f3187e67f4fd3ef15f73e91be2fad12. As real hardware testing (*) shows the above mentioned commit breaks U-Boot on it. Revert for the upcoming release. We may get more information in the future and optimize the code accordingly. (*) on Intel Edison board. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: Correct error return value in mrccache_get_region()Simon Glass
This function doesn't use uclass_find_first_device() correctly. Add a check that the device is found so we don't try to read properties from a NULL device. The fixes booting on minnoxmax. Fixes: 87f1084a630 ("x86: Adjust mrccache_get_region() to use livetree") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-19dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>Masahiro Yamada
The implementation of dma_map_single() and dma_unmap_single() is exactly the same for all the architectures that support them. Factor them out to <linux/dma-mapping.h>, and make all drivers to include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>. If we need to differentiate them for some architectures, we can move the generic definitions to <asm-generic/dma-mapping.h>. Add some comments to the helpers. The concept is quite similar to the DMA-API of Linux kernel. Drivers are agnostic about what is going on behind the scene. Just call dma_map_single() before the DMA, and dma_unmap_single() after it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19dma-mapping: fix the prototype of dma_unmap_single()Masahiro Yamada
dma_unmap_single() takes the dma address, not virtual address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19dma-mapping: fix the prototype of dma_map_single()Masahiro Yamada
Make dma_map_single() return the dma address, and remove the pointless volatile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-07x86: coral: Add I2C and TPM device-tree definitionsSimon Glass
Add nodes to the device tree for Cr50 and other available I2C ports. Also enable the ACPI interrupt driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Add support for ACPI general-purpose eventsSimon Glass
ACPI GPEs are used to signal interrupts from peripherals that are accessed via ACPI. In U-Boot these are modelled as interrupts using a separate interrupt controller. Configuration is via the device tree. Add a simple driver for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: itss: Add of-platdata supportSimon Glass
Allow this driver to be used in TPL by setting up the interrupt type correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Give each driver an IRQ typeSimon Glass
Add an IRQ type to each driver and use irq_first_device_type() to find and probe the correct one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: apl: Drop the I2C config in FSP-SSimon Glass
This config is not actually used here and in U-Boot it seems better to set this using the device tree for each individual controller. The monolithic config of the FSP-S is only necessary if the FSP is actually configuring something, but here it is not. The FSP-S does enable/disable the various I2C ports. It might be nice to handle this using the okay/disabled property of each port, but that can be considered later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: apl: Use the clock driverSimon Glass
Enable the Intel clock driver and modify coral's device tree to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Move P2SB from Apollo Lake to a more generic locationWolfgang Wallner
The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-04x86: itss: Remove apl-prefixWolfgang Wallner
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so remove the apl-prefix of the implemented functions/structures/... Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner
Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner
The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner
ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: limit the fs segment to the pointer sizeMasahiro Yamada
The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the comments about FS segement] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: use invd instead of wbinvd in real mode start codeMasahiro Yamada
I do not know why the boot code immediately after the system reset should write-back the cache content. I think the cache invalidation should be enough. I tested this commit with qemu-x86_defconfig, and it worked for me. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: serial: Use NS16550_DYNAMIC in Slim BootloaderPark, Aiden
Slim Bootloader provides serial port info in its HOB to support both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 or SYS_NS16550_PORT_MAPPED in U-Boot. To support both serial port configurations dynamically at runtime, Slim Bootloader serial driver leverages NS16550_DYNAMIC. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove the obsolete comments for data->type] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Move coreboot over to use the coreboot UARTSimon Glass
Use this UART to improve the compatibility of U-Boot when used as a coreboot payload. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: Update coreboot serial table structSimon Glass
Since mid 2016, coreboot has additional fields in the serial struct that it passes down to U-Boot. Add these so we are in sync. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-25asm: dma-mapping.h: Fix dma mapping functionsVignesh Raghavendra
Subsystems such as USB expect dma_map_single() and dma_unmap_single() to do dcache flush/invalidate operations as required. For example, see see drivers/usb/gadget/udc/udc-core.c::usb_gadget_map_request(). Currently drivers do this locally, (see drivers/usb/dwc3/ep0.c, drivers/mtd/nand/raw/denali.c etc..) Update arch specific dma_map_single() and dma_unmap_single() APIs to do cache flush/invalidate operations, so that drivers need not implement them locally. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-01-17common: Move hang() to the same header as panic()Simon Glass
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move ll_boot_init() to init.hSimon Glass
This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07x86: apl: Avoid accessing the PCI bus before it is probedSimon Glass
The PCI bus is not actually probed by the time the ofdata_to_platdata() method is called since that happens in the uclass's post_probe() method. Update the PMC and P2SB drivers to access the bus in its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-15x86: Add chromebook_coralSimon Glass
Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add FSP supportSimon Glass
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add FSP structuresSimon Glass
These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add Kconfig and MakefileSimon Glass
Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add P2SB driverSimon Glass
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add SPL/TPL initSimon Glass
Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add a CPU driverSimon Glass
Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add SPL loadersSimon Glass
Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add PUNIT driverSimon Glass
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add PCH driverSimon Glass
Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add LPC driverSimon Glass
This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add ITSS driverSimon Glass
This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add hostbridge driverSimon Glass
This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add systemagent driverSimon Glass
This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add pinctrl driverSimon Glass
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-18 05:58:09 +0000