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2012-01-13X86: Increase the size of the phys_size_t and phys_addr_t typesGabe Black
These types should be 64 bits long to reflect the fact that physical addresses and the size of physical areas of memory are more than 32 bits long. BUG=None TEST=Built and booted on Lumpy. Change-Id: I58bc69051db027d6eb718ec1c92a3d4afa2b7561 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14150 Reviewed-by: Simon Glass <sjg@chromium.org>
2011-11-03Clean up MTRR 7 right before jumping to the kernelStefan Reinauer
This cleans up the rom caching optimization implemented in coreboot (and needed throughout u-boot runtime. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:6585 TEST=boot coreboot on stumpy Change-Id: I7242c9c2b0546c633be8fb8ebc815ed6e6fda4d1 Reviewed-on: https://gerrit.chromium.org/gerrit/11138 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-27Use new VBNV section in coreboot tableStefan Reinauer
... rather than parsing the coreboot option table BUG=none TEST=boot tested on Stumpy Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I0814dd6c37cf826fda55a0f4acd6a1763b0626db Reviewed-on: https://gerrit.chromium.org/gerrit/10758 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-10-20Import the glibc implementation of x86 memset into u-bootGabe Black
I ran four iterations with the two implementations and used Vadim's CBMEM infrastructure to measure the time they took. These are all in microseconds, and the timestamp portion of the raw output of cbmem.py is included in the bug. The new implementation is about twice as fast as the old. Old: 1. 418,286 2. 418,302 3. 418,298 4. 418,290 New: 1. 184,800 2. 194,629 3. 194,188 4. 192,718 BUG=chrome-os-partner:6487 TEST=Booted on Stumpy. Change-Id: Iba398929cbba395e10851d676ae9d356ae670f41 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/10284 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-10-04console: Implement pre-console bufferGraeme Russ
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped. Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Change-Id: I3c4caad276b9e981ebea0a0fb79d85ee3a3bcb7d Reviewed-on: http://gerrit.chromium.org/gerrit/8686 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-03Process all cbmem table references consistently.Vadim Bendebury
A few CBMEM table entries are included in coreboot to let u-boot discover the locations of those entries. They all are passed using the same structure within coreboot table. This patch makes use of that structure for all communicated entries (timestam, console and MRC cache). It does not make sense to keep types of pointers in the sysinfo table, as nobody but the respective users of those fields use the types. Let's keep the pointers as void *, this also allows to reduce the amount of include files in systinfo.h and hide the timestamp structures in timestamp.c. BUG=chrome-os-partner:4200 TEST=manual . build the new firmware and program it on a stumpy . restart the machine . after it comes up to ChromeOS, run the cbmem.py utility Observe that timstamp values are displayed, and there is an entry with index 1000 (added by u-boot to the coreboot timestamp table). Change-Id: Icb808145c4c62cee939eceb3d5bf5afb3bcd00d9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8711 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-09-27Fix global data offset macros which are used in assemblyGabe Black
global_data.h defines a number of offset constants which are used by assembly to access the global data structure. These were partially correct but out of date. This change corrects them. BUG=None TEST=Built and booted twostop on Alex. Change-Id: I0989ee7dae0ef095af54b6df9137e925da3e74a6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/8395 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Ready: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-09-24Refactor hw timer code to accommodate execution tracing.Vadim Bendebury
This CL separates the HW timestamp acquisition into an inline function and provides interface to set the base time (to be retrieved from coreboot table). BUG=chromium-os:20733 TEST=manual . build the new firmaware image . bring up a stumpy with the new image to ChromeOS . examine crossystem reported timer values. Observe that the values start with zero and increase monotonously. Change-Id: I4ede0a55112e061e9d3790f01c8ca41a8539364b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8215 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-09-24Retrieve timestamp table information from coreboot table.Vadim Bendebury
This change adds code to process the timestamp table infiormation in case it is included in the coreboot table. coreboot/timestamp.h had to be modified to make it possible to compile in u-boot environment. The upcoming change will modify the timestamp handling code borrowed from coreboot under http://gerrit.chromium.org/gerrit/8164. BUG=chromium-os:20733 TEST=manual . brought up a stumpy to ChromeOS login screen. Change-Id: I008b5e4c971cbb13de2f055f53da6384035df5eb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/8222 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Gabe Black <gabeblack@chromium.org>
2011-09-22Make coreboot / chromeos config more similar to ARM configs.Stefan Reinauer
Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:6077 TEST=none Change-Id: I417ea3da24dc0cff17aa83ef799fabe78e4b1da5 Reviewed-on: http://gerrit.chromium.org/gerrit/8143 Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@google.com>
2011-09-19Don't spam POST80 codes with slow IO functionsStefan Reinauer
This patch prevents u-boot from "spamming" random progress codes on a port 80 "post card". The previous version of this patch just removed the delays in the "slow" IO functions, as they do not need to be slow, however, this patch is less intrusive. It uses another unused port that is often used by BIOSes (and the Linux Kernel) for small delay timing purposes. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=none TEST=boot coreboot+u-boot, see the right post codes come up. Change-Id: I9d1cc6de4472f5bb1f7b5ec6959273bfbfaa760b Reviewed-on: http://gerrit.chromium.org/gerrit/7778 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com>
2011-09-06Fix AHCI driver to operate on Intel controllers.Vadim Bendebury
First - make sure the ahci driver compiles and links properly when building for x86 platforms. Then it turned out that when trying to use AHCI driver on an x86 platform with an Intel AHCI controller, the driver does not operate properly if the requested amount of blocks to read was exceeding 255. It is probably possible to specify 0 as the block count and the driver will read 256 blocks, but it was decided to limit the number of blocks read at once to 128 (it should be a power of 2 for the optimal performance of solid state drives). BUG=chromium-os:19837 TEST=manual . program updated image (including vbexport SATA support extension) on an Alex. . restart the machine and enter `vboot_twostop' at u-boot prompt. Observe ChromeOS booting all the way to login screen. Change-Id: I7224ca14ae60f414db6dbe9e2f0a649312a9459c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/7232 Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2011-08-30Pass correct VDAT address to the vboot wrapper.Vadim Bendebury
On X86 systems where VDAT address is passed to the kernel through ACPI the u-boot must retrieve the address from the coreboot table and make it available to the vboot wrapper. This change accomplishes just that utilizing the coreboot changes which include the vdat area address and size into the coreboot table. Another modification is removing conditional compilation for including fields in the sysinfo table. The thing is that the code is not conditionally compiled anyways, so keeping an extra pointer in a table even if not needed is not a problem. BUG=chrome-os-partner:5707 TEST=manual . program the new firmware on an Alex . bring up ChromeOS . try running crossystem It was reporting errors before (when displaying data retrieved from VDAT). It displays sensible values now. Change-Id: Ib4090049092f7963a1b1705409d2beea8a9abfac Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/6868 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/6919 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-29Refactor the zboot underpinnings so they can be reused with a vboot imageGabe Black
If vboot successfully verifies a kernel, it will leave it in place and basically ready to boot. The zeropage table which is part of the x86 boot protocol is at the end of the kernel, though, instead of the beginning, and because the image is already in place there's no need to copy it around. This change refactors the code which implements the zboot command so that the configuration of the zeropage table and loading the pieces of the kernel into memory are done separately. Also, because the command line goes before the zeropage table in vboot which is somewhat incompatible with the normal protocol, where to put the command line is a now a parameter instead of being hard coded. BUG=chrome-os-partner:4552 TEST=Built and booted a legacy kernel with both the 32 bit and 16 bit boot protocols. Like other, earlier changes to this code only a current kernel which doesn't exercise old protocol features was tested. This change is more significant than the others and so may break booting old kernels. Also, the bootm command was not tested on x86. We need to decide if that command makes any sense to keep/support. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I09f6d0e2d46b4ce499f31c8073571968dba51b8a Reviewed-on: http://gerrit.chromium.org/gerrit/5545 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Fix device tree corruption problem.Vadim Bendebury
The problem turned out to be due to inconsistent compile flag settings when compiling the same include file in different .c files. BUG=chromium-os:19263 TEST=manual Build and run coreboot on Alex. It used to crash before this change in case gd was located at fixed address, it comes to the u-boot prompt now. Change-Id: Ia34284630b865ef715f1f6d0061620f1d6643b7b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/6206 Reviewed-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Enable OF_CONTROL for Alex.Vadim Bendebury
This change makes the Alex u-boot use configuration settings coming from the device tree supplied by coreboot through the coreboot table. The device tree now includes the necessary console configuration information. Code is added to retrieve the device tree pointer from the coreboot table, the appropriate coreboot structures and tag values are being duplicated in arch/i386/include/asm/ic/coreboot/tables.h. The pointer to the FDT is added to the global data structure, it is initialized as soon as it is retrieved from the coreboot table. For some reason placing the global data structure anywhere but in the .data segment causes the system to crash. This phenomenon will be investigated shortly, this commit is an intermediate step to get the device tree handover used by other coreboot/u-boot contributors. Core retrieving the device tree from CBFS is not needed anymore and gets removed. BUG=chrome-os-partner:5248 TEST=manual . build the new image and program it on Alex . restart the target, observe the console output The target boots all the way to u-boot prompt. Change-Id: I087cf70362ede0873be37fa5a98aa66a0b979d8f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/6132 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-08-29Include types.h explicitly in the i386 version of io.hGabe Black
The i386 version of io.h depends on the phys_addr_t type which is defined in types.h. It wasn't including that explicitly, and was working presumably because the other files including it had already included types.h themselves directly or indirectly. This change fixes that. BUG=chrome-os-partner:4722 TEST=Built and booted on x86-alex. Change-Id: I4a4a0b12bcadd807bc87a17219f705bfa5ae98e3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/5375 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-08-29Add GPIO parsing on coreboot+uboot comboStefan Reinauer
BUG=chrome-os-partner:3912 TEST=run vboot_twostop and see cros_gpio output Change-Id: Ic926765afa5b7d56ed475dc4c9e39a0dc99bcdf0 Reviewed-on: http://gerrit.chromium.org/gerrit/5292 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org>
2011-08-29Implement vbnv support.Vadim Bendebury
Using the tables defined by coreboot retrieve and cache information of where the VBNV area is kept in the CMOS. Populate VBNV access functions to actually read and write this area. BUG=chrome-os-partner:4552 TEST=manual . built and booted u-boot on an Alex. . compiled u-boot for kaen. . verified using some extra code that vbnv area is reported as 16 bytes at offset 52 (0x34). Change-Id: Icf6a54e12b7458af9f9c213b4afe30437565706b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://gerrit.chromium.org/gerrit/5079 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-08-29Add some header files with stub implementations/definitions that vboot needs.Gabe Black
BUG=chrome-os-partner:4552 TEST=Built and booted u-boot on an Alex. Change-Id: I3d60b4e3c212976b160f0ca3a3b026a3945ca954 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/4702 Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-08-29Add a default x86 implementation for cleanup_before_linux.Gabe Black
This function provides an opportunity for some last minute cleanup and reconfiguration before control is handed over to Linux. It's possible this may need to do something in the future, but for now it's left empty. It's set up as a weak symbol so it can be overridden if necessary on a case by case basis. BUG=chrome-os-partner:4552 TEST=Built and booted u-boot on an Alex. Change-Id: Ia59436b2a9d499ff659b2f41668cf951f2f7d999 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/4698 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Add a pointer to the global data structure to point to the device tree.Gabe Black
This change adds a pointer to the global data structure in i386 to point to the device tree. This mirrors an identical pointer in ARM. BUG=chrome-os-partner:4993 TEST=Built and booted u-boot on an Alex. Change-Id: I96710993bb35327ce5c4aa78aa5da763dc72109e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/4696 Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
2011-08-29Add coreboot framebuffer support.Stefan Reinauer
hardcoded values for Alex, needs work. Early adopters version. BUG=chrome-os-partner:4522 TEST=build coreboot, have a console on your screen Change-Id: I0d9a4abac51bb0c17a085d96d3f8ddec9a72985c Reviewed-on: http://gerrit.chromium.org/gerrit/3411 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com>
2011-08-29Extra information strings from the coreboot tables.Gabe Black
This change makes the coreboot parsing code record the location of informational strings to potentially display later. The code used to just ignore them. BUG=chrome-os-partner:3907 TEST=Built and booted on an Alex with an instrumented version of u-boot that printed out the strings, verified that the strings were reasonable. Change-Id: I0623cc5009278b8564ff631d572deb73ffd857a1 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/3223 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Allow compiling out realmode/bios code.Gabe Black
This change adds support for a CONFIG_NO_REALMODE_CODE config option that excludes the realmode/bios code other than reset code from the build. BUG=chrome-os-partner:3913 TEST=Built and booted with this option turned on and off. Change-Id: Ia248d491d7d67c5c3119129742c449d8246b7d43 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/3221 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Add support for booting Linux using the 32 bit boot protocol.Gabe Black
This change conditionally modifies the zboot command so that it can use the 32 bit boot protocol. This is necessary because the 16 bit realmode entry point assumes that it can call BIOS services which neither coreboot nor u-boot provide. BUG=chrome-os-partner:4700 TEST=Built and booted using the legacy and 32 bit boot protocols. Used dmesg to verify that the e820 memory map was successfully picked up by the kernel when using the 32 bit protocol. Change-Id: Ibd7d0989a2bef16affb1c3dd268ef9a72461597f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/3220 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Add infrastructure to extract an e820 table from the coreboot tables.Gabe Black
BUG=chrome-os-partner:3906 TEST=Printed out information from the tables on Alex. Change-Id: I29d635bbfa76bc2a48ad8e15011a5e03f86e56e0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/3218 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Clean up the i386 zimage code in preparation to extend it.Gabe Black
This change cleans up some formatting issues in the zimage handling code, and converts it from using offsets added to a base pointer to using the available structure definitions which were already being included. BUG=chrome-os-partner:3906 TEST=Successfully boot into chromeos on Alex. Change-Id: I2790d28355ca262f114c1538c3a64802d52ccea5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/3217 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Import code from coreboot's libpayload to parse the coreboot table.Gabe Black
BUG=chrome-os-partner:3906 TEST=Booted and verified that the table parsing function didn't return an error. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: I835c8982e5a1b5acfd0c82e064e844815c326f1c Reviewed-on: http://gerrit.chromium.org/gerrit/3118 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Tell u-boot about PCI bus 0 when initializing the coreboot "board".Gabe Black
U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. BUG=chrome-os-partner:4511 TEST=Booted into u-boot through coreboot, ran the pci command, and saw a reasonable looking scan of bus 0. Change-Id: Id3689625e40106c37a273c8409883d1515fcfaa9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/2603 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-29Add some missing includes.Gabe Black
I suspect these includes where usually available because something else included them earlier or because they were brought in transitively. BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Change-Id: Ib3de0d30b3707dd2469322b639224addb23839da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://gerrit.chromium.org/gerrit/2185 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24Remove the prototype for the unused function board_init.Gabe Black
BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Idac7d917f921cbcb5d11ca24ade062558e2d5304 Reviewed-on: http://gerrit.chromium.org/gerrit/2018 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-08-24Move the SC520 specific pci.h header into an sc520 directory.Gabe Black
The arch/i386/include/asm/ic/pci.h header file include definitions which were not generic to i386 and where specifically for SC520. This change moves that header into a directory which more accurately reflects that. BUG=chrome-os-partner:3905 TEST=Built coreboot u-boot. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: Icb4774f5c8d280904bbe1fa5cba42bdce002fcc0 Reviewed-on: http://gerrit.chromium.org/gerrit/2016 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
2011-04-13x86: Rename i386 to x86Graeme Russ
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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