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2016-10-19Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2016-10-19 Highlights this time around: - Add run time service (power control) support for PSCI (fixed in v3) - Add efi gop pointer exposure - SMBIOS support for EFI (on ARM) - efi pool memory unmap support (needed for 4.8) - initial x86 efi payload support (fixed up in v2) - various bug fixes Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/tables_csum.h
2016-10-19cpu: Add get_vendor callbackAlexander Graf
The CPU udevice already has a few callbacks to retreive information about the currently running CPUs. This patch adds a new get_vendor() call that returns the vendor of the main CPUs. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-19x86: Move smbios generation into arch independent directoryAlexander Graf
We will need the SMBIOS generation function on ARM as well going forward, so let's move it into a non arch specific location. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-19x86: Move table csum into separate fileAlexander Graf
We need the checksum function without all the other table functionality soon, so let's split it out into its own C file. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-18x86: Add implementations of setjmp() and longjmp()Simon Glass
Bring in these functions from Linux v4.4. They will be needed for EFI loader support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-18x86: Move table csum into separate headerAlexander Graf
We need the checksum function without all the other table functionality soon, so let's split it out into its own header file. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-11x86: Drop unused init_helper functionsSimon Glass
Drop init_bd_struct_r() which is no-longer used. Also drop the declaration for init_func_spi() since this is now handled by generic board init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11dm: x86: Move link to use driver model for videoSimon Glass
Update the configuration to use the new driver. Drop the existing plumbing code and unused header files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11x86: Add an accelerated memmove() functionSimon Glass
Bring in a faster memmove() from Linux 4.7. This speeds up scrolling on the display. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11x86: Fix Linux v4.7+ zimage booting (update bootparam.h)Stefan Roese
Booting Linux kernel v4.7+ does not work since Linux kernel commit 974f221c "x86/boot: Move compressed kernel to the end of the decompression buffer". This patch adds the latest version of the setup_header struct, adding "init_size" which is needed since this commit referenced above. With this patch, booting Linux v4.8-rc8 does work again on x86 boards. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-09-23Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada
Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-08-30x86: efi: Fix EFI 64-bit payload build warningsBin Meng
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16i2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail)Stefan Roese
This patch adds support for the SMBus block read/write functionality. Other protocols like the SMBus quick command need to get added if this is needed. This patch also removed the SMBus related defines from the Ivybridge pch.h header. As they are integrated in this driver and should be used from here. This change is added in this patch to avoid compile breakage to keep the source git bisectable. Tested on a congatec BayTrail board to configure the SMSC2513 USB hub. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16x86: cache.h: Add default for CONFIG_SYS_CACHELINE_SIZEStefan Roese
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE if it's undefined. This is needed for the xhci driver to compile. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-12x86: baytrail: acpi: Hide internal UART per GNVS settingBin Meng
If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12x86: acpi: Pack global NVS into ACPI tableBin Meng
Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12x86: quark: Introduce ACPI global NVSBin Meng
This introduces quark-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12x86: baytrail: Introduce ACPI global NVSBin Meng
This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30x86: quark: Add platform ASL filesBin Meng
This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30x86: quark: Prepare device.h for inclusion by ASLBin Meng
There is a device.h for quark on-chip devices, mainly for definitions of internal PCI device numbers, but it's not ready to be included by ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30x86: acpi: Make irqroute.asl commonBin Meng
The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30x86: acpi: Create a common irqlinks ASL fileBin Meng
Move the irqlinks.asl file currently in the BayTrail directory to a common place to be shared among all x86 platforms. As the PIRQ routing control programming interface is common to Intel chipsets, leave the common part in the common file, and move the platform specific part to the platform files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: baytrail: Add GPIO ASL descriptionBin Meng
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: baytrail: Add internal UART ASL descriptionBin Meng
BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file. Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPMBin Meng
Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers. However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode. U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start. To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: Prepare configuration tables in dedicated high memory regionBin Meng
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini
- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into cmd/qemu_fw_cfg.c - Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h - Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23x86: baytrail: Add platform ASL filesBin Meng
This adds basic BayTrail platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for now. They will be added in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Return table length in acpi_create_madt_lapics()Bin Meng
Like other MADT table write routines, make acpi_create_madt_lapics() return how many bytes it has written instead of the table end addr. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Add some generic ASL librariesBin Meng
This adds several generic ASL libraries that can be included by other ASL files, which are: - debug.asl: for debug output using POST I/O port and legacy serial port - globutil.asl: for string compare routines - statdef.asl: for _STA status values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Clean up table header revisionsBin Meng
The comment of initializing table header revision says: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ which might mislead it may increase per ACPI spec revision. However this is not the case. It's actually a fixed number as defined in ACPI spec, and in the laest ACPI spec 6.1, some table header revisions are still 1. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Use u32 in table write routinesBin Meng
Use u32 instead of unsigned long in the table write routines, as other routines do. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Adjust order in acpi_table.cBin Meng
Rearrange the routine order a little bit, to follow the order in which ACPI table is defined in acpi_table.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Change fill_header()Bin Meng
Rename fill_header() to acpi_fill_header() for consistency. Change its signature to remove the 'length' parameter and make it a public API. Also remove the unnecessary include files, and improve the AmlCode[] comment a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Remove acpi_create_ssdt_generator()Bin Meng
This acpi_create_ssdt_generator() currently does nothing. Remove this for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Reorder code in acpi_table.hBin Meng
Reorder the ACPI tables appearance by following the order: RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the table flag defines accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Various changes to acpi_table.hBin Meng
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID. - Do not typedef acpi_header_t, instead use struct acpi_table_hader. - Use a shorter name aslc_id and aslc-revision. - Change MCFG base address to use 32-bit value pairs (_l and _h). - Apply ACPI_APIC_ prefix to MADT APIC type macros and make their names to be more readable. - Apply __packed to struct acpi_madt_irqoverride and struct acpi_madt_lapic_nmi tables, as they are not naturally aligned by the compiler which leads to wrong sizeof(struct). - Rename model to res1 as it is reserved after ACPI spec 1.0. - Apply ACPI_ prefix to the PM profile macros and change them to enum. - Add ospm_flags to FACS structure which is defined since ACPI 4.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: acpi: Remove unused codesBin Meng
- Remove #include <> header files. - Remove APM_CNT register defines, which should not be here as they are SMI related. - Remove MP_IRQ_ defines as they are duplicates of the same ones in asm/mpspec.h. - Remove ACTL register defines, which should not be here as they are chipset specific. - Remove functional fixed hardware defines, which are not used. - Remove dev_scope related defines, which are not used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23x86: irq: Enable SCI on IRQ9Bin Meng
By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2016-05-23x86: Drop asm/acpi.hBin Meng
Remove asm/acpi.h which is never used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Add common SDRAM-init codeSimon Glass
The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common PCH code into a common placeSimon Glass
The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add a function to set the IOAPIC IDSimon Glass
Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass
Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add power-control supportSimon Glass
Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add an LPC driverSimon Glass
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass
GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a PCH driverSimon Glass
Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add basic support for broadwellSimon Glass
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
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