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u-boot-toradex.git
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toradex_ti-u-boot-2021.01_bringup
toradex_ti-u-boot-2023.04
toradex_ti-u-boot-2024.04
U-Boot bootloader for Apalis and Colibri modules
Toradex
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riscv
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Author
2018-12-31
riscv: bootm: Support booting VxWorks
Bin Meng
2018-12-18
riscv: Remove ae350.dts
Bin Meng
2018-12-18
riscv: bootm: Change to use boot_hart from global data
Bin Meng
2018-12-18
riscv: Save boot hart id to the global data
Bin Meng
2018-12-18
riscv: Adjust the _exit_trap() position to come before handle_trap()
Bin Meng
2018-12-18
riscv: Return to previous privilege level after trap handling
Bin Meng
2018-12-18
riscv: Fix context restore before returning from trap handler
Bin Meng
2018-12-18
riscv: Move trap handler codes to mtrap.S
Bin Meng
2018-12-18
riscv: Do some basic architecture level cpu initialization
Bin Meng
2018-12-18
riscv: Add indirect stringification to csr_xxx ops
Bin Meng
2018-12-18
riscv: Update supports_extension() to use desc from cpu driver
Bin Meng
2018-12-18
riscv: Add exception codes for xcause register
Bin Meng
2018-12-18
riscv: Add CSR numbers
Bin Meng
2018-12-18
riscv: Remove non-DM version of print_cpuinfo()
Bin Meng
2018-12-18
riscv: Probe cpus during boot
Bin Meng
2018-12-18
riscv: Enlarge the default SYS_MALLOC_F_LEN
Bin Meng
2018-12-18
riscv: qemu: Add platform-specific Kconfig options
Bin Meng
2018-12-18
riscv: Implement riscv_get_time() API using rdtime instruction
Anup Patel
2018-12-18
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
Bin Meng
2018-12-18
riscv: Introduce a Kconfig option for machine mode
Anup Patel
2018-12-18
riscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng
2018-12-18
riscv: qemu: Create a simple-bus driver for the soc node
Bin Meng
2018-12-18
riscv: add Kconfig entries for the code model
Lukas Auer
2018-12-05
riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
Rick Chen
2018-12-05
riscv: Add kconfig option to run U-Boot in S-mode
Anup Patel
2018-12-02
riscv: efi: Generate Microsoft PE format compliant images
Bin Meng
2018-11-26
riscv: cache: Implement i/dcache [status, enable, disable]
Rick Chen
2018-11-26
riscv: dts: Add ae350_32.dts for RV32I
Rick Chen
2018-11-26
riscv: dts: Sync to Linux Kernel ae350 dts.
Rick Chen
2018-11-26
riscv: align bootm implementation with that of other architectures
Lukas Auer
2018-11-26
riscv: save hart ID and device tree passed by prior boot stage
Lukas Auer
2018-11-26
riscv: do not blindly modify the mstatus CSR
Lukas Auer
2018-11-26
riscv: remove unused labels in start.S
Lukas Auer
2018-11-26
Drop CONFIG_INIT_CRITICAL
Bin Meng
2018-11-26
riscv: align mtvec on a 4-byte boundary
Lukas Auer
2018-11-26
riscv: fix inconsistent use of spaces and tabs in start.S
Lukas Auer
2018-11-26
riscv: implement the invalidate_icache_* functions
Lukas Auer
2018-11-26
riscv: hang on unhandled exceptions
Lukas Auer
2018-11-26
riscv: treat undefined exception codes as reserved
Lukas Auer
2018-11-26
riscv: complete the list of exception codes
Lukas Auer
2018-11-26
riscv: do not reimplement generic io functions
Lukas Auer
2018-11-26
riscv: make use of the barrier functions from Linux
Lukas Auer
2018-11-26
riscv: fix use of incorrectly sized variables
Lukas Auer
2018-11-26
riscv: enable -fdata-sections
Lukas Auer
2018-11-26
riscv: set -march and -mabi based on the Kconfig configuration
Lukas Auer
2018-11-26
riscv: add Kconfig entries for the C and A ISA extensions
Lukas Auer
2018-11-26
riscv: select CONFIG_PHYS_64BIT on RV64I systems
Lukas Auer
2018-11-26
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
Lukas Auer
2018-11-20
Use _AC and UL macros from linux/const.h
Baruch Siach
2018-11-18
Kbuild: add LDFLAGS_STANDALONE
Daniel Schwierzeck
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