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2011-11-22UPSTREAM: Reduce build timesWolfgang Denk
U-Boot Makefiles contain a number of tests for compiler features etc. which so far are executed again and again. On some architectures (especially ARM) this results in a large number of calls to gcc. This patch makes sure to run such tests only once, thus largely reducing the number of "execve" system calls. Example: number of "execve" system calls for building the "P2020DS" (Power Architecture) and "qong" (ARM) boards, measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ================================== P2020DS 20555 15205 -26% qong 31692 14490 -54% As a result, built times are significantly reduced, typically by 30...50%. Change-Id: I6e8c7c37cd13c56cb64d0a410514f2b9dc2d5adb Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Albert Aribaud <albert.aribaud@free.fr> cc: Graeme Russ <graeme.russ@gmail.com> cc: Mike Frysinger <vapier@gentoo.org> (cherry picked from commit 77d94d2d86c055f015734cc4cd972a5de30fc5a2) Reviewed-on: https://gerrit.chromium.org/gerrit/11806 Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-10-04console: Implement pre-console bufferGraeme Russ
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped. Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Change-Id: I3c4caad276b9e981ebea0a0fb79d85ee3a3bcb7d Reviewed-on: http://gerrit.chromium.org/gerrit/8686 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-04console: Squelch pre-console output in console functionsGraeme Russ
There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Change-Id: If62863017eaa48915b721675a5d520f9caa7e5e0 Reviewed-on: http://gerrit.chromium.org/gerrit/8685 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-08-29usb: update API for multiple controllersVincent Palatin
Add the ability to have USB devices enumerated on several controllers BUG=chrome-os-partner:5043 TEST=Compile U-Boot Change-Id: If43d32d4dc90c15ba570e5b9f86641cbf60ce064 Reviewed-on: http://gerrit.chromium.org/gerrit/4951 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
2011-05-20powerpc/fsl_pci: Fix device tree fixups for newer platformsKumar Gala
We assumed that only a small set of compatiable strings would be needed to find the PCIe device tree nodes to be fixed up. However on newer platforms the simple rules no longer work. We need to allow specifying the PCIe compatiable string for each individual SoC. We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if the default isn't sufficient. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-19Minor coding style cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-05-13powerpc/mpc8xxx: reword max tCKmin messageYork Sun
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-13powerpc/85xx: fix compatible property for the L2 cache nodeTimur Tabi
The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-12PPC405EX CHIP_21 erratumSteven A. Falco
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
2011-05-10Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2011-04-30Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
2011-04-30Handle most LDSCRIPT setting centrallyScott Wood
Currently, some linker scripts are found by common code in config.mk. Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is sometimes in arch config.mk and sometimes in board config.mk. Some are found using an arch-specific rule for looking in CPUDIR, etc. Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds. Replace all of this -- except for a handful of boards that are actually selecting a linker script in a unique way -- with centralized ldscript finding. If board code specifies LDSCRIPT, that will be used. Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used. If neither of these are specified, then the central config.mk will check for the existence of the following, in order: $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds $(TOPDIR)/$(CPUDIR)/u-boot.lds Some boards (sc3, cm5200, munices) provided their own u-boot.lds that were dead code, because they were overridden by a CPUDIR u-boot.lds under the old powerpc rules. These boards' own u-boot.lds have bitrotted and no longer work -- these lds files have been removed. Signed-off-by: Scott Wood <scottwood@freescale.com> Tested-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-30mpc832x: add support for the mpc8321 based suvd3 boardHeiko Schocher
- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2011-04-29fsl-ddr: Fix mixed-case macro namesKyle Moffett
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc: eSPI and eSPI controller supportMingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi
Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi
The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc: use 'video-mode' environment variable to configure DIUTimur Tabi
Use the 'video-mode' environment variable (for Freescale chips that have a DIU display controller) to designate the full video configuration. Previously, the DIU driver used the 'monitor' variable, and it was used only to determine the output video port. The old definition of the "monitor" environment variable only determines which video port to use for output. This variable was set to a number (0, 1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port. The resolution was hard-coded into board-specific code. The Linux command-line arguments needed to be hard-coded to the proper video definition string. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-04-27powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock
A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips
versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu
The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang
The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala
The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve
Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Add device tree fixup for bman portalHaiying Wang
Fix fdt bportal to pass the bman revision number to kernel via device tree. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdbRamneek Mehresh
Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2011-04-27powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoCDipen Dudhat
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27powerpc/85xx: Change CS timing params before changing CS properties on IFCDipen Dudhat
To make sure that machine change operation work successfully, change timing parameters first before changing machine for chip select on IFC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc: fix implementation of out_8 to match the other out_XX functionsTimur Tabi
Signed-off-by: Timur Tabi <timur@freescale.com>
2011-04-27Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk
2011-04-27Don't grab memory for LCD if FB address is definedMinkyu Kang
If FB address is defined specific address then don't grab memory for LCD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <kumar.gala@freescale.com>
2011-04-25Respect memreserve regions specified in the device treeGrant Likely
If a regions is reserved in the fdt, then it should not be used. Add the memreserve regions to the lmb so that u-boot doesn't use them to store the initrd. Signed-off-by: Grant Likely <grant.likely@linaro.org>
2011-04-25Remove device tree booting dependency on CONFIG_SYS_BOOTMAPSZGrant Likely
The previous patch makes u-boot use the full accessible size of ram as the default boot mapped size if CONFIG_SYS_BOOTMAPSZ is not defined, which means boot_relocate_fdt() can be changed to depend solely on CONFIG_OF_LIBFDT. Signed-off-by: Grant Likely <grant.likely@linaro.org>
2011-04-25Default to bootm_size() when CONFIG_SYS_BOOTMAPSZ is not definedGrant Likely
This patch adds a function getenv_bootm_mapsize() for obtaining the size of the early mapped region accessible by the kernel during early boot. It defaults to CONFIG_SYS_BOOTMAPSZ, or if not defined, defaults to getenv_bootm_size(), which in turn defaults to the size of RAM. getenv_bootm_mapsize() can also be overridden with a "bootm_mapsize" environmental variable. Signed-off-by: Grant Likely <grant.likely@linaro.org>
2011-04-25Stop passing around bootmem_base value.Grant Likely
For the calls to boot_relocate_fdt(), boot_get_cmdline(), and boot_get_kbd(), the value of bootmem_base is always obtained by calling getenv_bootm_low(). Since the value always comes from the same source, the calling signature for those functions can be simplified by making them call getenv_bootm_low() directly. Signed-off-by: Grant Likely <grant.likely@linaro.org>
2011-04-20Merge branch 'phylib' of git://git.denx.de/u-boot-mmcWolfgang Denk
2011-04-20Revert "PowerPC: Add support for -msingle-pic-base"Wolfgang Denk
This reverts commit 39768f7715ed637ef02f49fc7de664cc1aaf14b3. Reson: it breaks a number of boards with embedded environment as the code size grows in some places.
2011-04-20fsl: Change fsl_phy_enet_if to phy_interface_tAndy Fleming
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum. This meant that drivers which used fsl_phy_enet_if to deal with PHY interfaces would have to convert between the two (or we would have to have them mirror each other, and deal with the ensuing maintenance headache). Instead, we switch all clients of fsl_phy_enet_if over to phy_interface_t, which should become the standard, anyway. Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20tsec: Convert tsec to use PHY LibAndy Fleming
This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-12Make STANDALONE_LOAD_ADDR configurable per boardWolfgang Denk
Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR and allow that the architecture-specific default value gets overwritten by defining the value in the board header file. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-04-11PowerPC: Add support for -msingle-pic-baseJoakim Tjernlund
-msingle-pic-base is a new gcc option for ppc and it reduces the size of my u-boot with 6-8 KB. While at it, add -fno-jump-tables too to save a few more bytes. -msingle-pic-base will be in gcc 4.6, however backported patches are available at http://bugs.gentoo.org/show_bug.cgi?id=347281 Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2011-04-11PowerPC: Move -fPIC flag to common placeJoakim Tjernlund
The -fPIC flag belongs with -mrelocatable, move it there. Also change -fPIC to -fpic as this produces smaller binaries. However, currently -mrelocatable promotes -fpic to -fPIC, a fix for this is in upcoming gcc 4.6 or you can apply this small patch to gcc: diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 8da8410..e4b8280 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -227,7 +227,8 @@ do { \ } \ \ else if (TARGET_RELOCATABLE) \ - flag_pic = 2; \ + if (!flag_pic) \ + flag_pic = 2; \ } while (0) #ifndef RS6000_BI_ARCH -- Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2011-04-10powerpc/85xx: Removed clearing of L2-as-SRAMFabian Cenedese
Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by: Fabian Cenedese <cenedese@indel.ch> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10fsl_esdhc: Deal with watermark level register related changesPriyanka Jain
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DSJiang Yutang
For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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