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T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Add support for Freescale T1024/T1023 SoC.
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T1024 and T1023:
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio,
the same way as T4240 rev 2.0.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So use IFC acessor functions instead of in_be32().
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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B4420 is a personality of B4860.
It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc
The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.
get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.
Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.
Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.
Signed-off-by: York Sun <yorksun@freescale.com>
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Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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- fix serdes definition for t2081.
- fix clock speed for t2081.
- update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080,
T2081 has no SATA.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.
So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock
DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
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A new valid setting case added for fman1, it uses platform frequency.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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CHASSIS2 architecture never fix clock groups for Cluster and hardware
accelerator like PME, FMA. These are SoC defined. SoC defines :-
- NUM of PLLs present in the system
- Clusters and their Clock group
- hardware accelerator and their clock group
if no clock group, then platform clock divider for FMAN, PME
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
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85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".
Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.
Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.
Cluster clock registers are reorganized to be easily indexed.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move the quantative easing fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
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Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.
PME and FMan blocks can take different PLLs, configured by RCW.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.
Also added relevant QE support defines unique to P1021.
The P1021 QE is shared on P1012, P1016, and P1025.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it. Also we only have one Fman so no need for the code to deal with
a second.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.
We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)
On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL. On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.
On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency. It should be synchronous with the platform
frequency. CPU frequency is based on platform frequency in synchronous
mode.
Also fix:
* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
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