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2017-05-10mips: bmips: add bcm6328-power-domain driver support for BCM63268Álvaro Fernández Rojas
This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10mips: bmips: add bcm6328-power-domain driver support for BCM6328Álvaro Fernández Rojas
This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10mips: bmips: add bcm6345-rst driver support for BCM63268Álvaro Fernández Rojas
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-rst driver support for BCM6328Álvaro Fernández Rojas
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-rst driver support for BCM6358Álvaro Fernández Rojas
This driver can control up to 32 resets. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-clk driver support for BCM63268Álvaro Fernández Rojas
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-clk driver support for BCM6328Álvaro Fernández Rojas
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-clk driver support for BCM6358Álvaro Fernández Rojas
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add NeufBox 4 (Sercomm) boardÁlvaro Fernández Rojas
This serves as an example for bcm6358-leds. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6358-led driver support for BCM6358Álvaro Fernández Rojas
This driver can control up to 32 serial leds. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add Comtrend VR-3032u bcm6328-ledsÁlvaro Fernández Rojas
This board has several LEDs attached to its BCM6328 led controller. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add Comtrend AR-5387un bcm6328-ledsÁlvaro Fernández Rojas
This board has several LEDs attached to its BCM6328 led controller. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6328-led driver support for BCM63268Álvaro Fernández Rojas
This driver can control up to 24 LEDs and supports HW blinking and serial leds. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6328-led driver support for BCM6328Álvaro Fernández Rojas
This driver can control up to 24 LEDs and supports HW blinking and serial leds. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add Huawei HG556a gpio-ledsÁlvaro Fernández Rojas
This board has several LEDs attached to gpio0. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-gpio driver support for BCM63268Álvaro Fernández Rojas
This SoC has one gpio bank divided into two 32 bit registers, with a total of 52 GPIOs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-gpio driver support for BCM6328Álvaro Fernández Rojas
This SoC has one gpio bank with a total of 32 GPIOs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10mips: bmips: add bcm6345-gpio driver support for BCM6358Álvaro Fernández Rojas
This SoC has one gpio bank divided into two 32 bit registers, with a total of 40 GPIOs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add BMIPS Comtrend VR-3032u boardÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add support for Broadcom MIPS BCM63268 SoC familyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add BMIPS Comtrend AR-5387un boardÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add support for Broadcom MIPS BCM6328 SoC familyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add BMIPS Huawei HG556a boardÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add support for Broadcom MIPS BCM6358 SoC familyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: add initial infrastructure for Broadcom MIPS SoCsÁlvaro Fernández Rojas
CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: allow using generic sysreset driversÁlvaro Fernández Rojas
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: call debug_uart_init right before board_init_fDaniel Schwierzeck
All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10MIPS: add support for generating u-boot.elfÁlvaro Fernández Rojas
Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-04-13board_f: Rename initdram() to dram_init()Simon Glass
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05board_f: Drop return value from initdram()Simon Glass
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Drop board_type parameter from initdram()Simon Glass
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-01-10mips: Use common _AC macro now.Tom Rini
MIPS no longer needs to have its own version of this macro now. Fixes: 2a6713b09b8d ("move UL() macro from armv8/mmu.h into common.h") Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-02libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORYMasahiro Yamada
Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option") allows us to skip memory setup of DTB, but a problem for ARM is that spin_table_update_dt() and psci_update_dt() are skipped as well if CONFIG_ARCH_FIXUP_FDT is disabled. This commit allows us to skip only fdt_fixup_memory_banks() instead of the whole of arch_fixup_fdt(). It will be useful when we want to use a memory node from a kernel DTB as is, but need some fixups for Spin-Table/PSCI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for x86: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-30MIPS: Fix map_physmem for cached mappingsPaul Burton
map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton
When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30mips: Let cache.h be included from assembly sourceMarek Vasut
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck
Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: reserve space for exception vectorsDaniel Schwierzeck
In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck
Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: factor out code for initial stack and global dataDaniel Schwierzeck
Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix ROM exception vectorsDaniel Schwierzeck
When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck
This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-10-31Fix spelling of "resetting".Vagrant Cascadian
Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-19efi: Use asmlinkage for EFIAPISimon Glass
This is required for x86 and is also correct for ARM (since it is empty). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2016-09-23Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada
Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-21MIPS: Hang if run on a secondary CPUPaul Burton
Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton
The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>