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2022-07-06aspeed/spl: Remove OVERLAY from linker scriptJoel Stanley
The generic arm linker script contains this section: .bss __rel_dyn_start (OVERLAY) : { ... } The (OVERLAY) syntax in the description causes the .bss section to be included in the NOR area of the image: $ objdump -t -j .bss spl/u-boot-spl SYMBOL TABLE: 0000c61c l d .bss 00000000 .bss 0000c640 l O .bss 00000040 __value.0 0000c68c g O .bss 00000000 __bss_end 0000c61c g O .bss 00000000 __bss_start 0000c680 g O .bss 0000000c stdio_devices This is what the custom linker script tries to avoid, as the NOR area is read-only. Remove the OVERLAY syntax to fix the BSS location: $ objdump -t -j .bss spl/u-boot-spl SYMBOL TABLE: 83000000 l d .bss 00000000 .bss 83000000 l O .bss 00000040 __value.0 0000c61c g O .bss 00000000 __image_copy_end 8300004c g O .bss 00000000 __bss_end 83000000 g O .bss 00000000 __bss_start 83000040 g O .bss 0000000c stdio_devices This restores the state of the linker script before the patch that fixed the linker lists issue. Fixes: f6810b749f2e ("aspeed/ast2600: Fix SPL linker script") Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06ARM: dts: ast2500: Update SDHCI nodesJoel Stanley
Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06ARM: dts: ast2600: Update SDHCI nodesJoel Stanley
Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06ARM: dts: ast2600-evb: Add I2C devicesJoel Stanley
The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7, and a LM75 temp sensor on bus 8. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06ARM: dts: ast2500-evb: Add I2C devicesJoel Stanley
The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable those busses we can test the I2C driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06ARM: dts: ast2600-evb: Remove redundant pinctrlJoel Stanley
Now that these are in the dtsi we don't need them in the EVB device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06ARM: dts: ast2600: Disable I2C nodes by defaultJoel Stanley
Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06ARM: dts: ast2600: Add I2C reset propertiesJoel Stanley
The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06ARM: dts: ast2600: Add I2C pinctrlEddie James
Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06arm: dts: k3-am625-*: Mark memory with u-boot,dm-splGeorgi Vlaev
Mark the memory node with u-boot,dm-spl so we can use it from early SPL on both R5 and A53. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06arm: mach-k3: common: Use ddr_init in spl_enable_dcacheGeorgi Vlaev
The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06arm: k3: j721e: add dynamic sf bus override support for j721eVaishnav Achath
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs() lookup functions according to bootmode selection, so as to support both QSPI and OSPI boot using the same build. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2022-07-05Convert CONFIG_KIRKWOOD_PCIE_INIT et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_KIRKWOOD_EGIGA_INIT CONFIG_KIRKWOOD_PCIE_INIT CONFIG_KIRKWOOD_RGMII_PAD_1V8 CONFIG_KM_DISABLE_PCIE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05nxp: config_fsl_chain_trust.h: Clean up and remove unused portionsTom Rini
The way that secure boot is implemented today on NXP ARM platforms does not reuse the elements found in include/config_fsl_chain_trust.h to construct CONFIG_SECBOOT but instead board header files have their environment setup as needed and then fsl_setenv_chain_of_trust() will set secureboot in the environment. Remove a large number of unused defines here. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05fsl_validate: Migrate SPL_UBOOT_KEY_HASH to KconfigTom Rini
Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As part of this, change fsl_secboot_validate(...) to check that it is passed a non-empty string, rather than non-NULL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05arch/Kconfig.nxp: Re-organize slightlyTom Rini
Make all of the CHAIN_OF_TRUST options be under a single menu and add a comment for the rest, so the resulting config file reads more clearly. Remove duplicate CHAIN_OF_TRUST options from board/congatec/common/Kconfig. Remove duplicate NXP_ESBC config questions and move to arch/Kconfig.nxp. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SYS_FSL_SFP_BE et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_SYS_FSL_SEC_MON et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_ESBC_HDR_LS et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_ESBC_HDR_LS CONFIG_ESBC_ADDR_64BIT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Convert CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR to KconfigTom Rini
This converts the following to Kconfig: CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05Rename CONFIG_PWM to CONFIG_PWM_S5P and move to KconfigTom Rini
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new symbol. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-30Merge tag 'u-boot-at91-2022.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.10 cycle: This feature set includes mostly fixes and alignments: DT alignment with Linux for sama7g5, removal of invalid eeprom compatibles, removal of extra debug_uart_init calls for all at91 boards, support for pio4 driver pioE bank, and other minor fixes and enhancements for sam9x60 and sama5d2_icp boards.
2022-06-30Merge tag 'versal-qspi-for-v2022.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Versal QSPI/OSPI changes for v2022.10 - Add new flash types - Add cadence ospi driver for Xilinx Versal
2022-06-30gpio: atmel_pio4: add support for PIO_PORTEMihai Sain
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC. Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-06-29spi: cadence_qspi: Enable apb linear mode for apb read & write operationsT Karthik Reddy
On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence-qspi: reset qspi flash for versal platformT Karthik Reddy
When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-28Convert CONFIG_USB_MAX_CONTROLLER_COUNT to KconfigTom Rini
This converts the following to Kconfig: CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28siemens: Move CONFIG_FACTORYSET to KconfigTom Rini
Introduce board/siemens/common/Kconfig and have it hold FACTORYSET to start with. Use select for this on the boards that need it. Cc: Anatolij Gustschin <agust@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28arm: samsung: Migrate a number of symbols to KconfigTom Rini
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than CONFIG_EXYNOS[45] - In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX - Migrate specific SoC CONFIG values to Kconfig - Use CONFIG_TARGET_x rather than CONFIG_x - Migrate other CONFIG_EXYNOS_x symbols to Kconfig - Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE - Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest of U-Boot usage. Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28arm: exynos: Remove old pwm backlight driverTom Rini
Remove the unused older exynos pwm backlight driver. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28arm: samsung: Remove dead LCD codeTom Rini
Since bb5930d5c97f ("exynos: video: Convert several boards to driver model for video") there have been no callers of any of the exynos_lcd_* family of functions. Remove these from the boards, and then remove unused logo and related code as well. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28Convert CONFIG_LBA48 et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_LBA48 CONFIG_SYS_64BIT_LBA Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28spl: Move SPL_LDSCRIPT defaults to one placeTom Rini
We want to keep all of the default values for SPL_LDSCRIPT in the same place both for overall clarity as well as not polluting unrelated config files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_TEGRA_GPU to KconfigTom Rini
This converts the following to Kconfig: CONFIG_TEGRA_GPU Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: ehci-fsl: Remove non-DM codeTom Rini
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EFLASH_PROTSECTORS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EFLASH_PROTSECTORS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28aspeed/ast2600: Fix SPL linker scriptJoel Stanley
The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove . prefix") changed the name of the linker list sections. As the Aspeed SPL linker wasn't in the tree yet, it missed the change. This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which Aspeed was copied from. Fixes: 442a69c14375 ("configs: ast2600: Move SPL bss section to DRAM space") Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-28ARM: dts: at91: sam9x60ek: fix eeprom compatibleEugen Hristev
The memory on this board is microchip 24aa025e48 which is compatible with at24c02 with a page size of 16. Fix the compatible accordingly. Reported-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28ARM: dts: at91: replace microchip, 24aa02e48 with atmel, at24c02Eugen Hristev
microchip,24aa025e48 does not exist in the bindings of this driver. It can be replaced with atmel,at24c02 which is a standard compatible and the memory is compatible with this one, depending on the page size. microchip 24aa02e48 has a page size of 8, while 24aa025e48 has a page size of 16 bytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28ARM: dts: at91: sama7g5/sama7g5ek: sync with kernel at91 5.19Eugen Hristev
Sync with at91 maintainer tree for-5.19 branch. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-06-28ARM: dts: sam9x60: fix compatible for qspi child nodeSergiu Moga
Change the compatible of the qspi child node to `jedec,spi-nor` so that it can be properly found when probing the bus. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-06-27armv8 SHA-256 using ARMv8 Crypto ExtensionsLoic Poulain
This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs that have support for the SHA-256 part of the ARM v8 Crypto Extensions. It greatly improves sha-256 based operations, about 17x faster on iMX8M evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27armv8 SHA-1 using ARMv8 Crypto Extensions:Loic Poulain
This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-24ARM: zynq: Fix size-cells for pl353 driverAmit Kumar Mahapatra
"size-cells" of the nand controller node should be 0 as the "reg" property of the nand device node contains the chip select number and not address information. The patch fixes the below compilation warning arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format): /axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix usb node drive strength and slew rateAshok Reddy Soma
As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb gorup pins. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix tps544/u3007 node descriptionMichal Simek
u3007 is removed in zynqmp-m-a2197-02-revA board and on zynqmp-m-a2197-03-revA it was renamed to v3022 at address 0x18. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f477796bcca6fce09168699a0498d792f4a54acf.1655287013.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Update tps53681 i2c addressMichal Simek
TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address is 7bit where c0h is 1100000 which is 0x60. This will fix issues reported by make dtbs that 0xc0 is above 7bit regular i2c address range. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Fix i2c addresses for vck190 SCMichal Simek
si570 is normally at 0x5d address and address is not aligned with address in node. 8T49N240 can't be at 0xd8 that's why it is shifter by one bit. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4fa86fffa9cb8abe633fbc5a9c55bea249b5edfb.1655287013.git.michal.simek@amd.com
2022-06-24arm64: zynqmp: Enable DP for kv260-revA boardMichal Simek
DP is enabled for revB and should be enabled for kv260-revA too. Changes in other boards were done by commit 8b82a3a7feb0 ("arm64: zynqmp: Enable DP driver for SOMs"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4e273bce3a8acf4495b67b702b1704acec8d9ccb.1654779436.git.michal.simek@amd.com
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