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2020-10-22Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22Merge branch '2021.01-rc' of https://github.com/lftan/u-bootTom Rini
- fix Gen5 enable of EMAC via FPGA
2020-10-21stm32mp: stm32prog: accept device without partitionPatrick Delaunay
When partitions are not available on a device the command stm32prog raises an error but a device can have no partition to check in init_device() and the command need to continue to the next part_id. This patch correct an issue for ram0 target, when block_dev and mtd are NULL. For example with the simple flashlayout file: Opt Part Name Type Device Offset Binary - 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32 - 0x03 ssbl Binary none 0x0 u-boot.stm32 P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb Fixes: ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21arm: stm32: cleanup arch gpio.hPatrick Delaunay
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21stm32mp: limit size of cacheable DDR in pre-reloc stagePatrick Delaunay
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21arm: socfpga: fix Gen5 enable of EMAC via FPGARalph Siemsen
An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- Assorted R-Car Gen3 updates
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774E1 SoCBiju Das
Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774B1 SoCBiju Das
Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: dts: mt8512: add usb related nodesChunfeng Yun
Add usb, usb phy, and fixed regulators nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-19ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
2020-10-16arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16arm: octeontx: Select CLKStefan Roese
Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-15Merge tag 'mmc-2020-10-14' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
2020-10-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
2020-10-14arm: enable DM_RNG on QEMU by defaultHeinrich Schuchardt
The EFI_RNG_PROTOCOL is needed for address randomization in Linux. We should provide it by default on QEMU. Reported-by: François Ozog <francois.ozog@linaro.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-14arm64: dts: a3720: add support for espressobin with populated emmcAndre Heider
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for emmc, since our dtsi is still based on downstream and sdhc0 is used for the sd card. Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14arm64: dts: armada-3720-espressobin: split common parts to .dtsiAndre Heider
Move most of the dts to the new common armada-3720-espressobin.dtsi file, just like Linux, but keep the current, downstream based, version. The dts itself is imported from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-10-14arm64: dts: armada-3720-espressobin: use Linux model/compatible stringsAndre Heider
Fix the actual board vendor and ease synching dts files from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14arm: mvebu: Initial iEi Puzzle-M801 supportLuka Kovacic
Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC. Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-12Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini
2020-10-12arm: dts: lx2160ardb: support eMMC HS400 modeYangbo Lu
Add properties related to eMMC HS400 mode. mmc-hs400-1_8v; bus-width = <8>; They had been already in kernel dts file since the first lx2160ardb dts patch. b068890 arm64: dts: add LX2160ARDB board support Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-09arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMCDalon Westergreen
Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: arria10: Add qts-filter for Arria10 socfpgaDalon Westergreen
Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Add mailbox retry supportLey Foon Tan
Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan
Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: mailbox: Support sending large mailbox commandChee Hong Ang
Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Always read mailbox responses before returning statusChee Hong Ang
Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Refactor mailbox timeout event handlingChee Hong Ang
Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See
Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang
Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: Use DM watchdog timerChee Hong Ang
All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Show reset state in SPLChee Hong Ang
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang
Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang
Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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